Datasheet

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SDAS098B − OCTOBER 1984 − REVISED JANUARY 1995
2−7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT FOR Q OUTPUTS
From Output
Under Test
Test
Point
500 Ω
S1
C
L
(see Note A)
7 V
500 Ω
LOAD CIRCUIT FOR D OUTPUTS
From Output
Under Test
Test
Point
1 kΩ
S1
C
L
(see Note A)
7 V
1 kΩ
1.3 V
1.3 V1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Timing
Input
Data
Input
1.3 V 1.3 V
3.5 V
3.5 V
0.3 V
0.3 V
High-Level
Pulse
Low-Level
Pulse
t
w
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PHZ
t
PLZ
0.3 V
t
PZL
t
PZH
1.3 V1.3 V
1.3 V
1.3 V
3.5 V
0.3 V
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note C)
Waveform 2
S1 Open
(see Note C)
[0 V
V
OH
V
OL
[3.5 V
0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
t
PHL
t
PLH
t
PLH
t
PHL
Input
Out-of-Phase
Output
(see Note B)
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
3.5 V
0.3 V
V
OL
V
OH
V
OH
V
OL
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. C
L
includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs, switch S1 is open.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, t
r
= t
f
= 2 ns, duty cycle = 50%.
Figure 1. Load Circuits and Voltage Waveforms