Datasheet

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  
  
SCLS423F − JUNE 1998 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, V
CC
= 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
T
A
= 25°C SN54AHC594 SN74AHC594
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
w
Pulse duration
RCLK or SRCLK high or low 5 5 5
ns
t
w
Pulse duration
RCLR
or SRCLR low 5.2 5.2 5.2
ns
SER before SRCLK↑ 3 3 3
SRCLK↑ before RCLK↑
†
5 5 5
t
su
Setup time
SRCLR
low before RCLK↑ 5 5 5
ns
t
su
Setup time
SRCLR high (inactive) before SRCLK↑ 2.9 3.3 3.3
ns
RCLR high (inactive) before RCLK↑ 3.2 3.7 3.7
t
h
Hold time SER after SRCLK↑ 2 2 2 ns
†
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift
register is one clock pulse ahead of the storage register.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
LOAD
T
A
= 25°C SN54AHC594 SN74AHC594
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
MIN TYP MAX MIN MAX MIN MAX
UNIT
f
max
C
L
= 15 pF 80* 120* 70* 70
MHz
f
max
C
L
= 50 pF 55 105 50 50
MHz
t
PLH
RCLK
Q
A
−Q
H
C
L
= 15 pF
4.6* 8* 1* 8.5* 1 8.5
ns
t
PHL
RCLK Q
A
−Q
H
C
L
= 15 pF
4.9* 8.2* 1* 8.8* 1 8.8
ns
t
PLH
SRCLK
Q
H
C
L
= 15 pF
5.4* 9.1* 1* 9.7* 1 9.7
ns
t
PHL
SRCLK Q
H′
C
L
= 15 pF
5.5* 9.2* 1* 9.9* 1 9.9
ns
t
PHL
RCLR Q
A
−Q
H
C
L
= 15 pF 6* 9.8* 1* 10.6* 1 10.6 ns
t
PHL
SRCLR Q
H′
C
L
= 15 pF 5.6* 9.2* 1* 10* 1 10 ns
t
PLH
RCLK
Q
A
−Q
H
C
L
= 50 pF
6.9 10.5 1 11.1 1 11.1
ns
t
PHL
RCLK Q
A
−Q
H
C
L
= 50 pF
8.1 11.9 1 13.1 1 13.1
ns
t
PLH
SRCLK
Q
H
C
L
= 50 pF
7.7 11.7 1 12.4 1 12.4
ns
t
PHL
SRCLK Q
H′
C
L
= 50 pF
8.4 12.5 1 13.9 1 13.9
ns
t
PHL
RCLR Q
A
−Q
H
C
L
= 50 pF 9.1 13.1 1 14.4 1 14.4 ns
t
PHL
SRCLR Q
H′
C
L
= 50 pF 8.5 12.4 1 14 1 14 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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