Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 14

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   

SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 6-V V

Operation

D Inputs Accept Voltages to 6 V

D Max t

of 10 ns at 5 V

description/ordering information

The ’AC74 devices are dual positive-edge-

triggered D-type flip-flops.

A low level at the preset (PRE

) or clear (CLR) input

sets or resets the outputs, regardless of the levels

of the other inputs. When PRE

and CLR are

inactive (high), data at the data (D) input meeting

the setup-time requirements is transferred to the

outputs on the positive-going edge of the clock

pulse. Clock triggering occurs at a voltage level

and is not directly related to the rise time of the

clock pulse. Following the hold-time interval, data

at D can be changed without affecting the levels

at the outputs.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − N Tube SN74AC74N SN74AC74N

SOIC − D

Tube SN74AC74D

AC74

SOIC − D

Tape and reel SN74AC74DR

AC74

−40°C to 85°C

SOP − NS Tape and reel SN74AC74NSR AC74

−40 C to 85 C

SSOP − DB Tape and reel SN74AC74DBR AC74

TSSOP − PW

Tube SN74AC74PW

AC74

TSSOP − PW

Tape and reel SN74AC74PWR

AC74

CDIP − J Tube SNJ54AC74J SNJ54AC74J

−55°C to 125°C

CFP − W Tube SNJ54AC74W SNJ54AC74W

−55 C to 125 C

LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

SN54AC74 . . . FK PACKAGE

(TOP VIEW)

SN54AC74 ...J OR W PACKAGE

SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

2CLK

2PRE

1CLK

1PRE

1CLR

2CLR

GND

NC − No internal connection

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Summary of content (23 pages)

PAGE 1
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND description/ordering information The ’AC74 devices are dual positive-edgetriggered D-type flip-flops.
PAGE 2
SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q L H X X H L H L X X H H† L Q L L X X L H† H H ↑ H H H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level.
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SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 µA IOH = −12 mA VOH IOH = −24 mA TA = 25°C TYP MAX 3V 2.9 4.49 2.9 2.9 4.5 V 4.4 5.49 4.4 4.4 5.5 V 5.4 5.49 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 MAX V 3V 0.002 0.1 0.1 0.
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SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 5 V"0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency SN54AC74 SN74AC74 MIN MIN 140 tw Pulse duration tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ MAX 95 MAX 125 PRE or CLR low 4.5 5.5 5 CLK 4.5 5.
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SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open TEST S1 tPLH/tPHL Open 500 Ω tw LOAD CIRCUIT VCC VCC 50% VCC Input 0V VOLTAGE WAVEFORMS tPHL tPLH 50% VCC VOH 50% VCC VOL VCC 50% VCC Timing Input 0V tPLH tPHL Out-of-Phase Output 50% VCC 50% VCC 0V In-Phase Output 50% VCC Input 50% VCC VOH 50% VCC VOL
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74AC74DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74AC74DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74AC74DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74AC74DR SOIC D 14 2500 367.0 367.0 38.0 SN74AC74DR SOIC D 14 2500 333.2 345.9 28.6 SN74AC74NSR SO NS 14 2000 367.0 367.0 38.0 SN74AC74PWR TSSOP PW 14 2000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.