Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Custom logic Scan test device with bus tranceiver and registers SOIC 28

SN54ABT8652, SN74ABT8652

SCAN TEST DEVICES

WITH OCTAL BUS TRANSCEIVERS AND REGISTERS

SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

SCOPE

 Family of Testability Products

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

Functionally Equivalent to ’F652 and

’ABT652 in the Normal-Function Mode

SCOPE

 Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, CLAMP,

and HIGHZ

– Parallel-Signature Analysis at Inputs

With Masking Option

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Even-Parity Opcodes

Two Boundary-Scan Cells Per I/O for

Greater Flexibility

State-of-the-Art

EPIC-

ΙΙ

 BiCMOS Design

Significantly Reduces Power Dissipation

Package Options Include Shrink

Small-Outline (DL) and Plastic

Small-Outline (DW) Packages, Ceramic

Chip Carriers (FK), and Standard Ceramic

DIPs (JT)

description

The ’ABT8652 scan test devices with octal bus

transceivers and registers are members of the

Texas Instruments SCOPE testability

integrated-circuit family. This family of devices

supports IEEE Standard 1149.1-1990 boundary

scan to facilitate testing of complex circuit-board

assemblies. Scan access to the test circuitry is

accomplished via the 4-wire test access port

(TAP) interface.

In the normal mode, these devices are functionally equivalent to the ’F652 and ’ABT652 octal bus transceivers

and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing

at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does

not affect the functional operation of the SCOPE octal bus transceivers and registers.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

CLKAB

SAB

OEAB

GND

TDO

TMS

CLKBA

SBA

OEBA

TDI

TCK

321

13 14

TDI

TCK

TMS

TDO

OEBA

SBA

CLKBA

CLKAB

SAB

OEAB

15 16 17 18

GND

28 27 26

SN54ABT8652 . . . JT PACKAGE

SN74ABT8652 . . . DL OR DW PACKAGE

(TOP VIEW)

SN54ABT8652 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 D D D D D D SN54ABT8652 . . . JT PACKAGE SN74ABT8652 . . . DL OR DW PACKAGE (TOP VIEW) Members of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard 1149.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 description (continued) Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and OEBA) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode).
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS 3 26 OEAB OEBA L L 1 28 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 27 SBA L 3 26 OEAB OEBA H H 26 OEBA H X H 1 28 2 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ 2 SAB L X X X 27 SBA X BUS B BUS A BUS A 3 OEAB X L L 28 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 27 SBA X X X STORAGE FROM A, B, OR A AND B 3 OEAB H 26
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 functional block diagram Boundary-Scan Register OEAB OEBA CLKBA SBA CLKAB SAB 3 26 28 27 1 2 C1 1D A1 4 25 C1 B1 1D One of Eight Channels Bypass Register Boundary-Control Register VCC 13 16 TDI VCC TMS TCK Instruction Register 14 15 TAP Controller Pin numbers shown are for the DL, DW, and JT packages.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 Terminal Functions TERMINAL NAME DESCRIPTION A1–A8 Normal-function A-bus I/O ports. See function table for normal-mode logic. B1–B8 Normal-function B-bus I/O ports. See function table for normal-mode logic. CLKAB, CLKBA GND OEAB, OEBA SAB, SBA Normal-function clock inputs. See function table for normal-mode logic. Ground Normal-function output-enable inputs.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 state diagram description The TAP controller is a synchronous finite state machine that provides test control signals throughout the device. The state diagram shown in Figure 2 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 register overview With the exception of the bypass register, any test register can be thought of as a serial-shift register with a shadow latch on each bit. The bypass register differs in that it contains only a shift register.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 data register description boundary-scan register The boundary-scan register (BSR) is 38 bits long. It contains one boundary-scan cell (BSC) for each normal-function input and two BSCs for each normal-function I/O (one for input data and one for output data).
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 bypass register The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path, thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4. TDI Bit 0 TDO Figure 4.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. sample boundary This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output terminals on each falling edge of TCK.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 parallel-signature analysis (PSA) MASKX Data appearing at the selected device input terminals is compressed into a 16-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input terminals is compressed into an 8-bit parallel signature in the shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 timing description All test operations of the ’ABT8652 are synchronous to TCK. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output terminals on the falling edge of TCK.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TCK Test-Logic-Reset Select-IR-Scan Select-DR-Scan Update-DR Exit1-DR ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Shift-DR Capture-DR Select-DR-Scan ÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Update-IR Shift-IR Capture-IR Select-IR-Scan Select-DR-Scan TAP Controller State Run-Test/Idle TDO Test-Lo
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL II VCC = 4 4.5 5V CLK, OEAB, OEBA, S, TCK MIN TA = 25°C TYP† MAX –1.2 3 2 2 IOH = –32 mA IOL = 48 mA 2* VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14) SN54ABT8652 SN74ABT8652 MIN MAX MIN MAX 100 0 100 UNIT fclock tw Clock frequency CLKAB or CLKBA 0 Pulse duration CLKAB or CLKBA high or low 3 3 MHz ns tsu th Setup time A before CLKAB↑ or B before CLKBA↑ 5
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (normal mode) (see Figure 14) SN54ABT8652 PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLKAB or CLKBA A or B B or A CLKAB or CLKBA B or A SAB or SBA B or A OEAB or OEBA B or A OEAB or OEBA B or
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (test mode) (see Figure 14) SN54ABT8652 PARAMETER fmax tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ FROM (INPUT) TO (OUTPUT) TCK TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO TCK↓ A or B TCK↓ TDO VCC = 5 V, TA = 25°C MIN TY
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SN54ABT8652, SN74ABT8652 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS AND REGISTERS SCBS122F – AUGUST 1992 – REVISED DECEMBER 1996 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V 1.5 V Timing Input 0V tw tsu 3V Input 1.5 V 1.5 V 3V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
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MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.
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