Datasheet

SN74ABT18502
SCAN TEST DEVICE
WITH 18-BIT REGISTERED BUS TRANSCEIVER
SCBS753 – FEBRUARY 2002
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The SN74ABT18502 scan test device with an 18-bit universal bus transceiver is a member of the
Texas Instruments SCOPE testability IC family. This family of devices supports IEEE Std 1149.1-1990
boundary scan to facilitate testing of complex circuit board assemblies. Scan access to the test circuitry is
accomplished via the four-wire test access port (TAP) interface.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The device can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB
and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB
is low, the
B outputs are active. When OEAB
is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow but uses the OEBA
, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test circuitry
is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs
boundary scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry can perform
other testing functions such as parallel signature analysis (PSA) on data inputs and pseudorandom pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/binary count
up (PSA/COUNT) instruction is also included to ease the testing of memories and other circuits where a binary
count addressing scheme is useful.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C LQFP – PM Tray SN74ABT18502PM ABT18502
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
‡
(normal mode, each register)
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L L L X B
0
§
L L ↑ LL
L L ↑ HH
L HXLL
L HXHH
H X X X Z
‡
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA
, LEBA, and CLKBA.
§
Output level before the indicated steady-state input
conditions were established