Datasheet

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PRBSINPUT
t
jit(pp)
V
OH
V
OL
PeaktoPeakJitter
OUTPUT
t
c(n)
t
jit(per)
= | t
c(n)
-1/fo |
ACTUAL
OUTPUT
1/fo
IDEAL
OUTPUT
V
OL
PeriodJitter
t
c(n)
t
c(n+1)
t
jit(cc)
= | t
c(n)
-t
c(n+1)
|
CycletoCycleJitter
V
CC
/2
CLOCKINPUT
1/fo
OUTPUT
V
A
V
B
V
CC
/2
V
A
-V
B
V
OH
V
OL
V
CC
/2
V
OH
V
OL
V
CC
/2
V
OH
V
A
- V
B
INPUTS
V
CM
0.4V 1.0V
SN65MLVD2
SN65MLVD3
SLLS767 – NOVEMBER 2006
A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.
B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 125-MHz 50 ± 1% duty cycle clock input.
D. Deterministic jitter and random jitter are measured using a 250-Mbps 2
15-1
PRBS input
Figure 4. Receiver Jitter Measurement Waveforms
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