Datasheet

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Y
Z
0 V or V
CC
1.62 kΩ , ±1%
V
Y
, or V
Z
t
c(n)
1/f0
0 V
0 V
Period Jitter
0 V
Peak to Peak Jitter
1/f0
PRBS INPUT
OUTPUT
V
Y
-V
Z
V
Y
-V
Z
CLOCK
INPUT
IDEAL
OUTPUT
ACTUAL
OUTPUT
V
CC
V
CC
/2
t
jit(per)
= t
c(n)
-1/f0
t
jit(pp)
0 V
V
CC
V
CC
/2
0 V
V
Y
-V
Z
V
Y
-V
Z
Cycle to Cycle Jitter
0 V
V
Y
- V
Z
OUTPUT
t
c(n)
t
c(n+1)
t
jit(cc)
= | t
c(n)
- t
c(n+1)
|
SN65MLVD047
SLLS606A – MARCH 2004 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Driver Maximum Steady State Output Voltage
A. All input pulses are supplied by an Agilent 8304A Stimulus System.
B. The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
D. Peak-to-peak jitter is measured using a 200 Mbps 2
15
– 1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
8