Datasheet

www.ti.com
TRUTH TABLE
(1)
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
7 V 7 V
300 kΩ 300 kΩ
Input Input
V
CC
50 Ω
300 kΩ
V
CC
7 V
EN,EN
5 Ω
V
CC
7 V
Output
ABSOLUTE MAXIMUM RATINGS
SN65LVDS048A
SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DIFFERENTIAL INPUT ENABLES OUTPUT
R
IN+
– R
IN–
EN EN R
OUT
V
ID
≥ 100 mV H
L or
V
ID
≤ –100 mV H L
OPEN
Open/short or terminated H
X All other conditions Z
(1) H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
over operating free-air temperature range (unless otherwise noted)
(1) (2)
UNIT
V
CC
Supply voltage range –0.3 V to 4 V
V
I
(R
IN+
, Input voltage range –0.3 V to 4 V
R
IN-
)
Enable input voltage (EN, EN ) –0.3 V to (V
CC
+0.3 V)
V
O
(R
OUT
) Output voltage –0.3 V to (V
CC
+0.3 V)
Bus-pin (R
IN+
, R
IN–
) electrostatic discharge
(3)
> 10 kV
Continuous power dissipation See Dissipation Rating Table
Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.
2
Submit Documentation Feedback