Datasheet

SN65LV1023A
SN65LV1224B
SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009 www.ti.com
PIN FUNCTIONS
PIN
I/O DESCRIPTION
DB PACKAGE RHB PACKAGE
SERIALIZER
18, 20, 23, 25 17, 19, 22, 24 AGND Analog circuit ground (PLL and analog circuits)
17, 26 16, 25 AV
CC
Analog circuit power supply (PLL and analog circuits)
LVTTL logic input. Low puts the LVDS serial output into the high-impedance state.
19 18 DEN
High enables serial data output.
15, 16 12, 13, 14, 15 DGND Digital circuit ground
3−12 32, 1−9 D
IN0
− D
IN9
Parallel LVTTL data inputs
21 20 D
O
− Inverting LVDS differential output
22 21 D
O
+ Noninverting LVDS differential output
27, 28 26, 27, 28, 29 DV
CC
Digital circuit power supply
LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs
24 23 PWRDN
into the high-impedance state, putting the device into a low-power mode.
LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of
the two pins is asserted high for 6 cycles of TCLK, the serializer initiates
SYNC1, transmission of a minimum 1026 SYNC patterns. If after completion of the
1, 2 30, 31
SYNC2 transmission of 1026 patterns SYNC continues to be asserted, then the
transmission continues until SYNC is driven low and if the time SYNC holds > 6
cycles, another 1026 SYNC pattern transmission initiates.
LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a
13 10 TCLK_R/F
TCLK rising-edge data strobe.
LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to
14 11 TCLK 66-MHz clock. TCLK strobes parallel data into the input latch and provides a
reference frequency to the PLL.
DESERIALIZER
1, 12, 13 10, 11, 28, 29, 30 AGND Analog circuit ground (PLL and analog circuits)
4, 11 1, 8, 9 AV
CC
Analog circuit power supply (PLL and analog circuits)
14, 20, 22 12, 13, 19, 21 DGND Digital circuit ground
21, 23 20, 22 DV
CC
Digital circuit power supply
LVTTL level output. LOCK goes low when the deserializer PLL locks onto the
10 7 LOCK
embedded clock edge.
LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a
high-impedance state, putting the device into a low-power mode. To initiate power
7 4 PWRDN
down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low,
the device is in the power down state.
LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an
2 31 RCLK_R/F
RCLK rising-edge data strobe.
9 6 RCLK LVTTL level output recovered clock. Use RCLK to strobe ROUTx.
LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL
3 32 REFCLK
frequency.
LVTTL logic input. Low places R
OUT0
−R
OUT9
and RCLK in the high-impedance
8 5 REN
state.
5 2 R
I
+ Serial data input. Noninverting LVDS differential input
6 3 R
I
– Serial data input. Inverting LVDS differential input
28−24, 19−15 27−23, 18−14 R
OUT0
−R
OUT9
Parallel LVTTL data outputs
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Product Folder Link(s): SN65LV1023A SN65LV1224B