Datasheet

RCLK
ODD R
OUT
EVEN R
OUT
80%
20%
80%
20%
t
TLH(L)
V
diff
t
THL(L)
R
L
10 pF
D
O
+
D
O
−
10 pF
V
diff
= (D
O
+) − (D
O
−)
80%
20%
80%
20%
t
TLH(C)
t
THL(C)
CMOS/TTL Output
15 pF
Deserializer
90%
10%
90%
10%
t
t(CLK)
TCLK
t
t(CLK)
3 V
0 V
SN65LV1023A
SN65LV1224B
www.ti.com SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009
Figure 5. Worst-Case Deserializer I
CC
Test Pattern
Figure 6. Serializer LVDS Output Load and Transition Times
Figure 7. Deserializer CMOS/TTL Output Load and Transition Times
Figure 8. Serializer Input Clock Transition Time
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