Datasheet

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PulseGenerator,
15 µsDuration,
1%DutyCycle
100 Ω
V
TEST
0V
15 µs
1.5ms
−V
TEST
DEVICE INFORMATION
LOGIC DIAGRAM (POSITIVE LOGIC)
2
4
3
1
DE
D
RE
R
A
B
7
6
1
2
3
4
8
7
6
5
R
RE
DE
D
V
CC
B
A
GND
D,PORDGKPACKAGE
(TOPVIEW)
SN65HVD485E
SLLS612C – JUNE 2004 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
PIN ASSIGNMENTS
FUNCTION TABLE
(1)
DRIVER RECEIVER
OUTPUTS
INPUT ENABLE DIFFERENTIAL INPUTS ENABLE OUTPUT
D DE V
ID
= V
A
– V
B
RE R
A B
H H H L V
ID
≤ – 0.2 V L L
L H L H –0.2 V < V
ID
< –0.01 V L ?
X L Z Z –0.01 V ≤ V
ID
L H
Open H H L X H Z
X Open Z Z Open circuit L H
X Open Z
(1) H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
9
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