Datasheet
SN65HVD252
SN65HVD253
SLLSE37 –JUNE 2010
www.ti.com
THERMAL INFORMATION
HVD252/53
THERMAL METRIC UNITS
8 PINS SOIC
q
JA
Junction-to-ambient thermal resistance
(1)
124.5
q
JC(top)
Junction-to-case(top) thermal resistance
(2)
55.9
q
JB
Junction-to-board thermal resistance
(3)
50.2
°C/W
y
JT
Junction-to-top characterization parameter
(4)
4.9
y
JB
Junction-to-board characterization parameter
(5)
46
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(6)
n/a
V
CC
= 5 V, T
J
= 27°C, R
L
= 60Ω,
R
S
at 0 V, Input to D a 500-kHz 189.1 mW
50% duty cycle square wave
P
D
Device power dissipation
V
CC
= 5.25 V, T
J
= 150°C, R
L
= 50Ω,
R
S
at 0 V, Input to D a 500-kHz 274.8 mW
50% duty cycle square wave
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
CANH 2.75 3.5 4.5
Bus output voltage See Figure 1, TXD = 0 V, S = 0 V, AB = 0 V (HVD253),
V
O(D)
V
(dominant) R
CM
= open, C
L
= open, R
L
= 60 Ω
CANL 0.5 1.5 2.25
V
O(R)
Bus output voltage (recessive) TXD = 3 V, S = 0 V No Load 2 2.5 3 V
See Figure 1, TXD = 0 V, S = 0 V, R
CM
= open,
1.5 2.4 3.4
C
L
= open, 45 Ω ≤ R
L
≤ 60 Ω
Differential output voltage
V
OD(D)
V
(dominant)
See Figure 1, TXD = 0 V, S = 0 V, R
L
= 60 Ω,
1.2 2.6 3.3
R
CM
= 330 Ω, C
L
= open, –5 V < V
CM
< 10 V
R
L
= 60 Ω –12 12
Differential output voltage See Figure 1, TXD = 3 V, S = 0 V,
V
OD(R)
mV
(recessive) R
CM
= open, C
L
= 100 pF
No load –100 50
Output symmetry (dominant or See Figure 1, S = 0 V, AB = 0 V (HVD253), R
CM
= open,
V
SYM
–400 0 400 mV
recessive) C
L
= open, R
L
= 60 Ω, V
SYM
= V
CC
– V
CANH
– V
CANL
–5 V < V
CANH
< 10 V, CANL open –350 2.5
Short-circuit steady-state output
I
OS(ss)
mA
current
–5 V < V
CANL
< 10 V, CANH open –2.5 350
(1) All typical values are at 25°C with V
CC
= 5 V.
DRIVER SWITCHING CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
pHR
Propagation delay time, high input to recessive output 50 70
t
pLD
Propagation delay time, low input to dominant output 40 70
See Figure 1, S = 0 V, R
L
= 60 Ω,
ns
C
L
= 100 pF, R
CM
= open
t
r
Differential output signal rise time, 10% to 90% 15 30
t
f
Differential output signal fall time, 90% to 10% 17 30
R
L
= 60 Ω, C
L
= 15 pF,
t
en
Enable time from silent mode to dominant 200 ns
C
LD
= 100 pF
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