Datasheet

Power Supply Decoupling Techniques and
BOARD LAYOUT
SN10501
SN10502
SN10503
SLOS408B – MARCH 2003 – REVISED JANUARY 2009 .................................................................................................................................................. www.ti.com
from the feedback loop by inserting a series isolation ground- and power-plane layout should not be in
resistor between the amplifier output and the close proximity to the signal I/O pins. Avoid
capacitive load. This does not eliminate the pole from narrow power and ground traces to minimize
the loop response, but rather shifts it and adds a zero inductance between the pins and the decoupling
at a higher frequency. The additional zero cancels the capacitors. The power supply connections should
phase lag from the capacitive-load pole, thus always be decoupled with these capacitors.
increasing the phase margin and improving stability. Larger (2.2- µ F to 6.8- µ F) decoupling capacitors,
effective at lower frequency, should also be used
on the main supply pins. These may be placed
Recommendations
somewhat farther from the device and may be
shared among several devices in the same area
Power-supply decoupling is a critical aspect of any of the PC board.
high-performance amplifier design process. Careful
3. Careful selection and placement of external
decoupling provides higher-quality ac performance,
components preserves the high frequency
most notably improved distortion performance. The
performance of the SN1050x. Choose
following guidelines ensure the highest level of
low-reactance resistors. Surface-mount resistors
performance.
work best, and allow a tighter overall layout.
1. Place decoupling capacitors as close to the Metal-film and carbon-composition axial-lead
power-supply inputs as possible, with the goal of resistors can also provide good high-frequency
minimizing the inductance of the path from performance. Again, keep component leads and
ground to the power supply PC-board trace length as short as possible.
Never use wirewound resistors in a high
2. Placement priority; locate the smallest-value
frequency application. Since the output pin and
capacitors nearest to the device.
inverting-input pin are the most sensitive to
3. Solid power and ground planes are
parasitic capacitance, always position the
recommended to reduce the inductance along
feedback and series-output resistor, if any, as
power-supply return-current paths, with the
close as possible to the output pin. Other network
exception of the areas underneath the input and
components, such as noninverting-input
output pins.
termination resistors, should also be placed close
4. Recommended values for power supply
to the package. Where double-sided component
decoupling include a bulk decoupling capacitor
mounting is allowed, place the feedback resistor
(6.8 to 22 µ F), a mid-range decoupling capacitor
directly under the package on the other side of
(0.1 µ F) and a high frequency decoupling
the board between the output and inverting input
capacitor (1000 pF) for each supply. A 100 pF
pins. Even with a low parasitic capacitance
capacitor can be used across the supplies as well
shunting the external resistors, excessively high
for extremely high-frequency return currents, but
resistor values can create significant time
often is not required.
constants that can degrade performance. Good
axial-lead metal-film or surface-mount resistors
have approximately 0.2 pF in shunt with the
resistor. For resistor values > 2.0 k Ω , this
Achieving optimum performance with a
parasitic capacitance can add a pole and/or a
high-frequency amplifier like the SN1050x requires
zero below 400 MHz that can affect circuit
careful attention to board layout parasitics and
operation. Keep resistor values as low as
external component types.
possible, consistent with load-driving
Recommendations to optimize performance include: considerations. A good starting point for design is
to set the R
f
to 1.3 k Ω for low-gain, noninverting
1. Minimize parasitic capacitance to any ac
applications. This automatically keeps the resistor
ground for all signal I/O pins. Parasitic
noise terms low, and minimizes the effect of their
capacitance on the output and inverting-input pins
parasitic capacitance.
can cause instability: on the noninverting input, it
can react with the source impedance to cause 4. Connections to other wideband devices on
unintentional band limiting. To reduce unwanted the board may be made with short, direct
capacitance, open a window in all ground and traces or through onboard transmission lines.
power planes around the signal I/O pins. Keep For short connections, consider the trace and the
ground and power planes unbroken elsewhere on input to the next device as a lumped capacitive
the board. load. Use relatively wide traces (50 mils to 100
mils), preferably with ground and power planes
2. Minimize the distance ( < 0.25 ” ) from the
opened up around them. Low parasitic capacitive
power-supply pins to high frequency 0.1-µ F
loads ( < 4 pF) may not need an R
(ISO)
, since the
decoupling capacitors. At the device pins, the
SN1050x is nominally compensated to operate
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Product Folder Link(s): SN10501 SN10502 SN10503