Datasheet
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Clock and Data Recovery
Minimum Transition Density
Jitter Tolerance
Jitter Generation
Loop Timing Mode
SLK2721
SLLS532B – JUNE 2002 – REVISED MARCH 2007
The CDR unit of the SLK2721 device recovers the clock and data from the incoming data streams.
In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency
stability. If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the
LOL pin is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm.
The loop filter transfer function is optimized to enable the CDR to track ppm difference in the clocking and
tolerate the minimum transition density that can be received in a SONET data signal ( ± 20 ppm). The transfer
function yields a typical capture time of 3500-bit times for random incoming NRZ data after the device is
powered up and achieves frequency locking.
The device tolerates up to 72 consecutive digits (CID) without sustaining an error.
Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that
causes the equivalent 1-dB optical/electrical power penalty. This refers to the ability of the device to withstand
input jitter without causing a recovered data error. The device has a jitter tolerance that exceeds the mask
shown in Figure 2 (GR-253 Figure 5-28). This jitter tolerance is specified using a pseudorandom data pattern of
2
31
–1.
OC-N/STS-N F0 F1 F2 F3 F4 A1 A2 A3
LEVEL (Hz) (Hz) (Hz) (kHz) (kHz) (Ulpp) (Ulpp) (Ulpp)
3 10 30 300 6.5 65 0.15 1.5 15
12 10 30 300 25 250 0.15 1.5 15
24 Not specified
48 10 600 6000 100 1000 0.15 1.5 15
Figure 2. Input Jitter Tolerance
The jitter of a serial clock and serial data outputs must not exceed 0.01 UI
rms
/0.1 UI
p-p
when a serial data with no
jitter is presented to the inputs. The measurement bandwidth for intrinsic jitter is 12 kHz to 20 MHz.
When LOOPTIME is high, the clock synthesizer used to serialize the transmit data is bypassed and the timing is
provided by the recovered clock. However, REFCLK is still needed for the recovery loop operation.
8
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