Datasheet

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ELECTRICAL CHARACTERISTICS
PTV08040W
SLTS257B – SEPTEMBER 2005 – REVISED JANUARY 2008
T
A
= 25 ° C, V
I
= 12 V, V
O
= 3.3 V, C
I
= 560 µF, C
O
= 150 F, and I
O
= I
O
max (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
25 ° C, Natural Convection 0 50
(1)
I
O
Output current 8 V ≤ V
I
≤ 14 V A
60 ° C, 200 LFM airflow 0 48
(1)
V
I
Input voltage range Over I
O
range 8 14 V
V
O
tol Set-point voltage tolerance ± 2
(2)
%V
O
Δ Reg
temp
Temperature variation – 40 ° C < T
A
< 85 ° C ± 0.5 %V
O
Δ Reg
line
Line regulation Over V
I
range ± 3 mV
Δ Reg
load
Load regulation Over I
O
range ± 3 mV
Δ Reg
tot
Total output variation Includes set-point, line, load, – 40 ° C ≤ T
A
≤ 85 ° C ± 3
(2)
%V
O
Δ Reg
adj
Output adjust range 0.8 3.6 V
R
SET
= 2.49 k Ω , V
O
= 3.3 V 95
R
SET
= 6.98 k Ω , V
O
= 2.5 V 93
R
SET
= 13.0 k Ω , V
O
= 2 V 92
R
SET
= 16.9 k Ω , V
O
= 1.8 V 91
η Efficiency I
O
= 35 A %
R
SET
= 27.4 k Ω , V
O
= 1.5 V 90
R
SET
= 53.6 k Ω , V
O
= 1.2 V 88
R
SET
= 113.0 k Ω , V
O
= 1 V 86
R
SET
= open circuit, V
O
= 0.8 V 82
V
O
ripple (peak-to-peak) 20-MHz bandwidth All voltages 15 mV
PP
I
O
trip Overcurrent threshold Reset, followed by auto-recovery 75 100 115 A
t
rr
1 A/µs load step, Recovery time 50 µs
Transient response
Δ V
tr
50 to 100% I
O
max, C
O
= 150 µF V
O
over/undershoot 140 mV
I
IL
track Track input current (pin 15) Pin to GND – 0.13
(3)
mA
dV
track
/dt Track slew rate capability C
O
≤ C
O
(max) 1 V/ms
V
I
Increasing 7.5
(4)
7.8
UVLO Undervoltage lockout threshold Pin 16 open V
V
I
Decreasing 6 6.5
(4)
Inhibit control (pin 16) Referenced to GND
V
IH
Input high voltage 2.5 Open
(5)
V
V
IL
Input low voltage – 0.2 0.5
I
IL
inhibit Input low current Pin to GND 0.5 mA
I
I
inh Input standby current Pin 16 to GND 35 mA
f
s
Switching frequency Over V
I
and I
O
ranges 900 1050 1200 kHz
C
I
External input capacitance 560
(6)
µF
Nonceramic 0 14,000
(7)
Capacitance value µF
C
O
External output capacitance Ceramic 150
(8)
750
Equivalent series resistance (nonceramic) 3
(9)
m Ω
2.7
MTBF Reliability Per Bellcore TR-332 50% stress, T
A
= 40 ° C, ground benigh
10
6
Hrs
(1) See SOA curves or consult factory for appropriate derating.
(2) The set-point voltage tolerance is affected by the tolerance of R
SET
. The stated limit is unconditionally met if R
SET
has a tolerance of 1%
with 100 ppm/ ° C or better temperature stability.
(3) This control pin has an internal pull-up to 5 V. A small, low-leakage (<100 nA) MOSFET or open-drain/collector voltage supervisor IC is
recommended to control this pin. For further information, see the related application section.
(4) These are the default voltages. They may be adjusted using the UVLO Prog control input. See the Application Information section for
further guidance.
(5) This control pin has an internal pull-up to 5 V. When left open-circuit the module operates when input power is applied. A small,
low-leakage (<100 nA) MOSFET is recommended to control this pin. For further information, see the related application section.
(6) A minimum capacitance of 560-µF is required at the input for proper operation. For best results, 1000 µF is recommended. The
capacitance must be rated for a minimum of 300 mArms of ripple current.
(7) This is the calculated maximum. The minimum ESR requirement often results in a lower value. For further information, see the related
application section.
(8) A minimum value of output capacitance is required for proper operation. Adding additional capacitance at the load further improves
transient response.
(9) This is the typical ESR for all the electrolytic (nonceramic) output capacitance. Use 5 m Ω as the minimum when using manufacturer's
max-ESR values to calculate.
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