Datasheet

PCM9211
www.ti.com SBAS495 –JUNE 2010
Register 30h, DIR Recovered System Clock (SCK) Ratio Setting
(Address: 30h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name RSV RSV RSV PSCKAUTO RSV PSCK2 PSCK1 PSCK0
Default Value 0 0 0 0 0 0 1 0
Memo
PSCKAUTO: PLL SCK Dividing Ratio Automatic Control Setting
0: Disable (default)
1: Enable
This register is used to set the PLL SCK dividing ratio automatic control function.
SCK setting is automatically set depending on the input sampling frequency.
512f
S
: 54 kHz and below
256f
S
: 54 kHz to 108 kHz
128f
S
: 108 kHz and above or unlocked
The register setting of PSCKAUTO is prioritized higher than the PSCK[2:0] register setting.
For instance, if PSCKAUTO = '1', the PSCK[2:0] register setting is ignored.
To use this function, the XTI clock source is required.
PSCK[2:0]: DIR Recovered Clock Frequency Setting
000: 128f
S
001: Reserved
010: 256f
S
(default)
011: Reserved
100: 512f
S
101: Reserved
110: Reserved
111: Reserved
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