Datasheet

PCM9211

www.ti.com

SBAS495 –JUNE 2010

(Address: 23h, Write and Read)

DATA B7 B6 B5 B4 B3 B2 B1 B0

Reg Name RSV RSV XTIWT1 XTIWT0 PRTPRO1 PRTPRO0 ERRWT1 ERRWT0

Default Value 0 0 0 0 0 1 0 0

Memo

XTIWT[1:0]: Crystal OSC, Oscillation Start-up Wait Time Setting

00: 25 ms

01: 50 ms

10: 100 ms

11: 200 ms

XTIWT is counted by the PLL generated clock.

These are the resulting values when the PLL is running with a free-run clock because of no S/PDIF input.

After these delay times, the Main Port source changes from DIR to ADC when DIR is unlocked.

PRTPRO[1:0]: Process for Parity Error Detection

00: No process

01: For PCM data only, an 8x continuous parity error is replaced by previous data and muted after ninth

parity error at EPARITY = 1 (default)

10: For PCM and non-PCM data, an 8x continuous parity error is replaced by previous data and muted

after ninth parity error at EPARITY = 1

11: Reserved (The definition of Non-PCM depends on the Non-PCM Definition Setting Register)

Validity flag, user bit, channel status, Non-PCM and DTS-CD detection should be refreshed by waiting

more than 192/f

without any parity error.

ERRWT[1:0]: ERROR Release Wait Time Setting

00: ERROR Release after 48 counts of preamble B (Default), 192 ms at f

= 48 kHz

01: ERROR Release after 12 counts of preamble B

10: ERROR Release after six counts of preamble B

11: ERROR Release after three counts of preamble B

These counts are only available when DIR is unlocked or DIR sampling frequency is changed or exceeds

limits defined by DIR Acceptable f

Range Setting and Mask registers.

CLKST also uses ERRWT to release.

Product Folder Link(s): PCM9211