Datasheet

SDA
SCL
Start Repeated Start Stop
t
BUF
t
D-SU
t
D-HD
t
LOW
t
SCL-F
t
S-HD
t
HI
t
S-SU
t
SCL-R
t
S-HD
t
SDA-R
t
SDA-F
t
P-SU
t
GW
PCM9211
SBAS495 –JUNE 2010 www.ti.com
Timing Diagram
Figure 43 shows the detailed timing diagram for SCL and SDA.
STANDARD MODE FAST MODE
SYMBOL DESCRIPTION MIN MAX MIN MAX UNITS
f
SCL
SCL clock frequency 100 400 kHz
t
BUF
Bus free time between STOP and START condition 4.7 1.3 µs
t
LOW
Low period of the SCL clock 4.7 1.3 µs
t
HI
High period of the SCL clock 4.0 0.6 µs
t
S-SU
Setup time for START/Repeated START condition 4.7 0.6 µs
t
S-HD
Hold time for START/Repeated START condition 4.0 0.6 µs
t
D-SU
Data setup time 250 100 ns
t
D-HD
Data hold time 0 3450 0 900 ns
t
SCL-R
Rise time of SCL signal 1000 20 + 0.1C
B
300 ns
t
SCL-F
Fall time of SCL signal 1000 20 + 0.1C
B
300 ns
t
SDA-R
Rise time of SDA signal 1000 20 + 0.1C
B
300 ns
t
SDA-F
Fall time of SDA signal 1000 20 + 0.1C
B
300 ns
t
P-SU
Setup time for STOP condition 4.0 0.6 µs
t
GW
Allowable glitch width n/a 50 ns
C
B
Capacitive load for SDA and SCL line 400 100 pF
Noise margin at High level for each connected device
V
NH
0.2 × V
DD
0.2 × V
DD
V
(including hysteresis)
Noise margin at Low level for each connected device
V
NL
0.1 × V
DD
0.1 × *V
DD
V
(including hysteresis)
V
HYS
Hysteresis of Schmitt-trigger input n/a 0.05 × V
DD
V
Figure 43. Control Interface Timing
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