Datasheet

3
21
3
21
646362
646362
3
21
3
21
DBCK
DSDRI
DSDLI
PCM9211
www.ti.com SBAS495 –JUNE 2010
Output Source Selection
The output source for Multi-Channel PCM Output (the Main output port and MPIO_B) is selected by a register.
Table 29 describes the relationship between the output source and the register (MCHRSRC) setting.
Table 29. Multi-Channel PCM Output Source and Register Setting
MCHRSRC
MULTI-CHANNEL MODE
OUTPUT SOURCE SELECT '00' or '10' '01' or '11'
CLOCK SOURCE MAIN OUT
(1)
MULTI-CH INPUT
DOUT MAIN OUT
(1)
MDIN0
MDOUT0 MAIN OUT
(1)
MDIN0
MDOUT1 Logic low MDIN1
MDOUT2 Logic low MDIN2
MDOUT3 Logic low MDIN3
(1) The Main OUT data source is discussed in the DIR section of this data sheet. It can either be the DIR
recovered clock and data, or the ADC DATA and the ADC clock source.
DSD Input Mode
The PCM9211 can also be used to suppress the jitter of the DSCKI signals, typically generated by an HDMI
receiver. DSD signals (DBCKI, DSDRI, DSDLI) are routed to the Main Port as DBCKO, DSDRO, and DSDLO,
respectively.
The DIT works with DSCKI for SCK, DBCKI for BCK, internally-created LRCK, DBCKI divided by 64, and '0' data
for DIN.
MOLRMTEN (Register 6Ah) can be used to mute/unmute DSDRO from the LRCK port. When MOLRMTEN is set
to '1', mute/unmute of DSDRO from LRCK is available by MODMUT = 1/0.
Table 30 summarizes the DSD input mode configuration. Figure 34 illustrates the DSD format.
Table 30. DSD Input Mode Summary
SIGNAL NAME MPIO GROUP / PIN DESCRIPTION
MPIO_C0 or
DSCKI SCK input (256f
S
)
MPIO_B0
MPIO_C1 or
DBCKI DBCK input for DSD format (64f
S
)
MPIO_B1
MPIO_C2 or
DSDRI R-channel DSD data input for DSD format
MPIO_B2
MPIO_C3 or
DSDLI L-channel DSD data input for DSD format
MPIO_B3
DSCKO SCKO SCK output generated by DIR from DIT output
DBCKO BCK DBCK output for DSD format (the same signal as DBCKI)
DSDRO LRCK R-channel DSD data output for DSD format (the same signal as DSDRI)
DSDLO DOUT L-channel DSD data output for DSD format(the same signal as DSDLI)
Figure 34. DSD Format
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