Datasheet

SystemClock
(SCK)
"L"
"H"
0.8V
2V
t
SCL
t
SCH
t
SCY
PCM9211
www.ti.com SBAS495 –JUNE 2010
ADC Details
System Clock
The system clock for the ADC of the PCM9211 must be either 256f
S
or 512f
S
, where f
S
is the audio sampling rate
for the ADC (16 kHz to 96 kHz).
Table 3 lists the typical system clock frequencies f
SCK
for common audio sampling rates. Figure 13 shows the
timing requirements for the system clock inputs.
Table 3. ADC Clock Requirements
BIT CLOCK FREQUENCY SYSTEM CLOCK FREQUENCY
SAMPLING FREQUENCY 64f
S
256f
S
512f
S
16 kHz 1.024 MHz 4.0960 MHz 8.1920 MHz
32 kHz 2.048 MHz 8.1920 MHz 16.3840 MHz
44.1 kHz 2.8224 MHz 11.2896 MHz 22.5792 MHz
48 kHz 3.072 MHz 12.2880 MHz 24.5760 MHz
88.2 kHz 5.6448 MHz 22.5792 MHz See
(1)
96 kHz 6.144 MHz 24.5760 MHz See
(1)
(1) This system clock frequency is not supported for the given sampling clock frequency
SYMBOL DESCRIPTION MIN MAX UNITS
t
SCY
System clock cycle time 30 ns
t
SCH
System clock high time 0.4 t
SCY
ns
t
SCL
System clock low time 0.4 t
SCY
ns
System clock duty cycle 40 60 %
Note: This timing requirement is applied when ADC clock source (Register 42h/ADCLK) is AUXIN0, AUXIN1 or AUXIN2.
Figure 13. ADC System Clock Input Timing
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Product Folder Link(s): PCM9211