Datasheet

PCM9211
www.ti.com SBAS495 –JUNE 2010
Register 75h, MPIO_B3, MPIO_B2 Output Flag Select
(Address: 75h, Write and Read)
DATA B7 B6 B5 B4 B3 B2 B1 B0
Reg Name MPB3FLG3 MPB3FLG2 MPB3FLG1 MPB3FLG0 MPB2FLG3 MPB2FLG2 MPB2FLG1 MPB2FLG0
Default Value 0 0 0 0 0 0 0 0
Memo
MPB3FLG[3:0]: MPIO_B3 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
MPB2FLG[3:0]: MPIO_B2 Pin, Flag Select
0000: CLKST (default)
0001: EMPH
0010: BPSYNC
0011: DTSCD
0100: PARITY
0101: LOCK
0110: VOUT
0111: UOUT
1000: COUT
1001: BFRAME
1010: FSOUT0
1011: FSOUT1
1100: FSOUT2
1101: FSOUT3
1110: INT0
1111: INT1
These register settings are effective only at MPBSEL[2:0] = '011', MPB3SEL = '0', and MPB2SEL = '0'.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 107
Product Folder Link(s): PCM9211