Datasheet
®
18
PCM3501
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
BCKP
BCK Period 600 ns
t
BCKH
BCK Pulse Width HIGH 200 ns
t
BCKL
BCK Pulse Width LOW 200 ns
t
FSW
FS Pulse Width HIGH t
BCKP
– 60 t
BCKP
t
BCKP
+ 60 ns
t
FSP
FS Period 1/f
S
t
FSSU
FS Set Up TIme to BCK Rising Edge 60 ns
t
FSHD
FS Hold TIme to BCK RIsing Edge 60 ns
t
DISU
DIN Set Up Time to BCK Rising Edge 60 ns
t
DIHD
DIN Hold Time to BCK Rising Edge 60 ns
t
CKDO
Delay Time BCK Falling Edge to DOUT 0 80 ns
t
HZDO
Delay Time BCK Falling Edge to DOUT Active 20 ns
t
DOHZ
Delay Time BCK Falling Edge to DOUT Inactive 19.5 ns
t
FSOW
FSO Pulse Width HIGH t
BCKP
– 60 t
BCKP
t
BCKP
+ 60 ns
t
BFSO
Delay Time BCK Falling Edge to FSO 0 80 ns
t
R
Rising Time of All Signals 30 ns
t
F
Falling Time of All Signals 30 ns
FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).
Table III shows the TSC pin settings and corresponding
mode selections. When Time Slot Mode is enabled, FSO
(pin 12) is used as a frame sync output, which is connected
to the FS input of the next PCM3501 in the Time Slot
sequence. Figures 13 and 14 provide detailed timing for
Time Slot Mode operation.
TSC (PIN 7) TIME SLOT MODE
0 Time Slot Mode Disabled, Normal Operation
1 Time Slot Operation Enable
LOOP (PIN 19) LOOP-BACK MODE
0 Loop-Back Mode Disabled, Normal Operation
1 Loop-Back Mode Enabled
TABLE IV. Loop-Back Mode Selection.
TABLE III. Time Slot Mode Selection.
HPFD (PIN 18) HIGH-PASS FILTER MODE
0 High-Pass Filter On
1 High-Pass Filter Off
TABLE V. High-Pass Filter Mode Selection.
HIGH-PASS FILTER
The PCM3501 includes a digital high-pass filter in the ADC
which may be used to remove the DC offset created by the
analog front-end (AFE) section. The high-pass filter response
is shown in Figure 15. The high-pass filter may be enabled or
disabled using the HPFD input (pin 18). Table V shows the
HPFD pin settings and corresponding mode selections.
ADC-TO-DAC LOOP BACK
The PCM3501 includes a Loop-Back Mode, which directly
feeds the ADC data to the DAC input. This mode is
designedfor diagnostic testing and system adjustment. Loop-
Back Mode is enabled and disabled using the LOOP input
(pin 19). Table IV shows the LOOP pin settings and corre-
sponding mode selections. The serial interface continues to
operate in Loop-Back Mode, allowing the host to read the
ADC data at the DOUT pin.
t
FSW
t
FSSU
High Impedance
High Impedance
t
FSHD
t
BCKP
t
BCKL
t
DISU
t
DIHD
t
BCKH
t
CKDO
t
HZDO
t
DOHZ
t
FSP
NOTES: Timing measurement reference level is (V
IH
/V
IL
)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
0.5V
DD
t
FSOW
t
BFSO
FS
(input)
BCK
(input)
DIN
(input)
DOUT
(output)
FSO
(output)