Datasheet

t
h(WS)
WCLK
BCLK
DOUT
DIN
t
L(BCLK)
t
H(BCLK)
t
s(WS)
t
d(DO-WS)
t
d(DO-BCLK)
t
h(DI)
t
s(DI)
PCM3070
www.ti.com
SLAS724 FEBRUARY 2011
Figure 4. I
2
S/LJF/RJF Timing in Slave Mode
Table 3. I
2
S/LJF/RJF Timing in Slave Mode (see Figure 4)
PARAMETER IOVDD=1.8V IOVDD=3.3V UNITS
MIN MAX MIN MAX
t
H
(BCLK) BCLK high period 35 35 ns
t
L
(BCLK) BCLK low period 35 35
t
s
(WS) WCLK setup 8 8
t
h
(WS) WCLK hold 8 8
t
d
(DO-WS) WCLK to DOUT delay (For LJF mode only) 20 20
t
d
(DO-BCLK) BCLK to DOUT delay 22 22
t
s
(DI) DIN setup 8 8
t
h
(DI) DIN hold 8 8
t
r
Rise time 4 4
t
f
Fall time 4 4
© 2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): PCM3070