Datasheet

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AML: Multiplexer Input Channel Selection (ADC)
PG[4:0]: PGA Gain Selection (ADC)
BYP: HPF Bypass Control (ADC)
PCM3052A
SLES160 – NOVEMBER 2005
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 72 0 1 0 0 1 0 0 0 RSV RSV AML PG4 PG3 PG2 PG1 PG0
Default value: 0
AML MULTIPLEXER INPUT CHANNEL SELECTION
0 Line (default)
1 Microphone
The AML bit selects the input channel of multiplexer.
Default value: 0 0100 (–4 dB)
PG[4:0] PGA Gain Selection PG[4:0] PGA Gain Selection
11111 Digital mute 01111 7 dB
11110 Digital mute 01110 6 dB
11101 Digital mute 01101 5 dB
11100 20 dB 01100 4 dB
11011 19 dB 01011 3 dB
11010 18 dB 01010 2 dB
11001 17 dB 01001 1 dB
11000 16 dB 01000 0 dB
10111 15 dB 00111 – 1 dB
10110 14 dB 00110 –2 dB
10101 13 dB 00101 –3 dB
10100 12 dB 00100 –4 dB (default)
10011 11 dB 00011 Digital mute
10010 10 dB 00010 Digital mute
10001 9 dB 00001 Digital mute
10000 8 dB 00000 Digital mute
The PG[4:0] bits control the gain of PGA for adjusting the signal level for ADC.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
REGISTER 75 0 1 0 0 1 0 1 1 RSV RSV RSV RSV BYP 1 RSV RSV
Default value: 0
BYP = 0 Normal output, HPF enable (default)
BYP = 1 Bypass output, HPF disable
The BYP bit controls HPF function; dc components of input and dc offset are converted in bypass mode.
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