Datasheet

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BCKIN
LRCIN
DIN
t
(BCH)
t
(BCL)
t
(LRP)
t
(LB)
t
(BCY)
0.5 V
DD
t
(BL)
DOUT
t
(BDO)
t
(LDO)
0.5 V
DD
t
(DIS)
t
(DIH)
0.5 V
DD
0.5 V
DD
T0021−01
SYSTEM CLOCK
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN pulse cycle time t
(BCY)
300 ns (min)
BCKIN pulse duration, HIGH t
(BCH)
120 ns (min)
BCKIN pulse duration, LOW t
(BCL)
120 ns (min)
BCKIN rising edge to LRCIN edge t
(BL)
40 ns (min)
LRCIN edge to BCKIN rising edge t
(LB)
40 ns (min)
LRCIN pulse duration t
(LRP)
t
(BCY)
(min)
DIN setup time t
(DIS)
40 ns (min)
DIN hold time t
(DIH)
40 ns (min)
DOUT delay time to BCKIN falling edge t
(BDO)
40 ns (max)
DOUT delay time to LRCIN edge t
(LDO)
40 ns (max)
Rising time of all signals t
(RISE)
20 ns (max)
Falling time of all signals t
(FALL)
20 ns (max)
Figure 33. Audio Data Input/Output Timing
The system clock for the PCM3006 must be either 256 f
S
, 384 f
S
or 512 f
S
, where f
S
is the audio sampling
frequency. The system clock should be provided to SYSCLK (pin 9).
The PCM3006 also has a system clock detection circuit that automatically senses if the system clock is operating
at 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divded into 256 f
S
automatically. The 256-f
S
clock is used to operate the digital filter and the delta-sigma modulator.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 34
illustrates the system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY
(kHz) MHz
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.3840
44.1 11.2896 16.9344 22.5792
48 12.2880 18.4320 24.5760
18