Datasheet

PCM2912A
SLES230 SEPTEMBER 2008 ..........................................................................................................................................................................................
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TERMINAL FUNCTIONS
TERMINAL
NAME PJT I/O DESCRIPTIONS
BGND 1 Reference for internal regulator.
V
BUS
2 Connect to USB power (V
BUS
)
D 3 I/O USB differential input/output minus
(1)
D+ 4 I/O USB differential input/output plus
(1)
V
DD
5 Digital power supply
(2)
DGND 6 Digital ground
XTO 7 O Crystal oscillator output
XTI 8 I Crystal oscillator input
(3)
FL 9 External filter pin of L-channel (optional)
FR 10 External filter pin of R-channel (optional)
Common voltage for ADC, DAC, and analog front-end (V
CCA
/2). Decoupling capacitor should be connected to
V
COM1
11
AGND.
V
COM2
12 Common voltage for headphone (V
CCA
/2). Decoupling capacitor should be connected to AGND.
AGND 13 Analog ground
NC 14 Not connected
V
CCA
15 Analog power supply
V
IN
16 I ADC microphone input
MBIAS 17 O Microphone bias output (0.75 V
CCA
)
V
OUT
L 18 O Headphone output for L-channel
V
CC
L 19 Analog power supply for headphone amplifier of L-channel
(2)
HGND 20 Analog ground for headphone amplifier
V
CC
R 21 Analog power supply for headphone amplifier of R-channel
(2)
V
OUT
R 22 O Headphone output for R-channel
MAMP 23 I Microphone preamplifier gain control (LOW: Preamplifier off, HIGH: Preamplifier on = +20 dB)
(3)
POWER 24 I Power consumption declaration select pin (LOW: 100 mA, HIGH: 500 mA)
(3)
PGND 25 Analog ground for microphone bias, microphone amplifier, and PGA
V
CCP
26 Analog power supply for PLL
(2)
TEST1 27 I Test pin. Must be set to HIGH
(3)
TEST0 28 I Test pin. Must be set to LOW
(3)
SSPND 29 O Suspend flag (LOW: Suspend, HIGH: Operational state)
MMUTE 30 I Microphone mute control, active HIGH (LOW: Mute off, HIGH: Mute on)
(4)
REC 31 O Status output for record (LOW: Record, FLASH: Mute on recode, HIGH: Stop)
(5)
PLAY 32 O Status output for playback (LOW: Playback, FLASH: Mute on playback, HIGH: Stop)
(5)
(1) LV-TTL level
(2) Connect decouple capacitor to corresponding ground.
(3) 3.3-V CMOS level input.
(4) 3.3-V CMOS level input with internal pulldown.
(5) 5-V tolerant, open-drain.
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