Datasheet

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Audio Serial Interface
Audio Data Formats and Timing
t
w(BCH)
DOUT
t
w(BCL)
t
(LB)
t
(BCY)
LRCK
BCK
50%ofV
IO
50%ofV
IO
50%ofV
IO
t
(CKDO)
t
(LRDO)
T0010-12
t
(BL)
PCM1870
SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007
The audio serial interface of the PCM1870 consists of LRCK, BCK and DOUT. Sampling rate (f
S
), left and right
channel are present on LRCK. DOUT transmits the serial data from the decimation filter for the ADC. BCK is
used to transmit the serial audio data on DOUT at its high-to-low transition. BCK and LRCK should be
synchronized with audio system clock. Ideally, it is recommended that they are derived from it.
The PCM1870 requires LRCK to be synchronized with the system clock. The PCM1870 do not need a specific
phase relationship between LRCK and the system clock.
The PCM1870 has both master mode and slave mode interface formats, which can be selected by register 84
(MSTR). LRCK and BCK are generated from the system clock in master mode.
The PCM1870 supports I
2
S, right-justified, left-justified, and DSP formats. The data formats are shown in
Figure 16 , and they are selected using resister 70 (RFM[1:0], PFM[1:0]). All formats require binary
2s-complement, MSB-first audio data. The default format is I
2
S. Figure 14 shows a detailed timing diagram.
PARAMETERS SYMBOL MIN MAX UNIT
BCK pulse cycle time (I
2
S, left- and right-justified formats) t
(BCY)
1/(64f
S
)
(1)
BCK pulse cycle time (DSP format) t
(BCY)
1/(256f
S
)
(1)
BCK high-level time t
w(BCH)
35 ns
BCK low-level time t
w(BCL)
35 ns
BCK rising edge to LRCK edge t
(BL)
10 ns
LRCK edge to BCK rising edge t
(LB)
10 ns
DOUT delay time from BCK falling edge t
(CKDO)
40 ns
(1) f
S
is the sampling frequency.
Figure 14. Audio Interface Timing (Slave Mode)
16 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): PCM1870