Datasheet

5−7
5.8 Secondary Clock Control Register
The secondary clock control register is used to control the secondary clock outputs.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Secondary clock control
Type R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Register: Secondary clock control
Type: Read-only, Read/Write
Offset: 68h
Default: 0000h
Table 5−8. Secondary Clock Control Register Description
BIT TYPE FUNCTION
15−14 R Reserved. These bits return 0 when read.
13 R/W
S_CLKOUT9 disable.
0 = S_CLKOUT9 enabled (default).
1 = S_CLKOUT9 disabled and driven high.
12 R/W
S_CLKOUT8 disable.
0 = S_CLKOUT8 enabled (default).
1 = S_CLKOUT8 disabled and driven high.
11 R/W
S_CLKOUT7 disable.
0 = S_CLKOUT7 enabled (default).
1 = S_CLKOUT7 disabled and driven high.
10 R/W
S_CLKOUT6 disable.
0 = S_CLKOUT6 enabled (default).
1 = S_CLKOUT6 disabled and driven high.
9 R/W
S_CLKOUT5 disable.
0 = S_CLKOUT5 enabled (default).
1 = S_CLKOUT5 disabled and driven high.
8 R/W
S_CLKOUT4 disable.
0 = S_CLKOUT4 enabled (default).
1 = S_CLKOUT4 disabled and driven high.
7−6 R/W
S_CLKOUT3 disable.
00, 01, 10 = S_CLKOUT3 enabled (00 is the default).
11 = S_CLKOUT3 disabled and driven high.
5−4 R/W
S_CLKOUT2 disable.
00, 01, 10 = S_CLKOUT2 enabled (00 is the default).
11 = S_CLKOUT2 disabled and driven high.
3−2 R/W
S_CLKOUT1 disable.
00, 01, 10 = S_CLKOUT1 enabled (00 is the default).
11 = S_CLKOUT1 disabled and driven high.
1−0 R/W
S_CLKOUT0 disable.
00, 01, 10 = S_CLKOUT0 enabled (00 is the default).
11 = S_CLKOUT0 disabled and driven high.