Datasheet

3−5
Table 3−2. PCI S_AD31−S_AD16 During the Address
Phase of a Type 0 Configuration Cycle
DEVICE
NUMBER
SECONDARY IDSEL
S_AD31−S_AD16
S_AD
ASSERTED
0h 0000 0000 0000 0001 16
1h 0000 0000 0000 0010 17
2h 0000 0000 0000 0100 18
3h 0000 0000 0000 1000 19
4h 0000 0000 0001 0000 20
5h 0000 0000 0010 0000 21
6h 0000 0000 0100 0000 22
7h 0000 0000 1000 0000 23
8h 0000 0001 0000 0000 24
9h 0000 0010 0000 0000 25
Ah 0000 0100 0000 0000 26
Bh 0000 1000 0000 0000 27
Ch 0001 0000 0000 0000 28
Dh 0010 0000 0000 0000 29
Eh 0100 0000 0000 0000 30
Fh 1000 0000 0000 0000 31
10h−1Eh 0000 0000 0000 0000 −
3.4 Special Cycle Generation
The bridge is designed to generate special cycles on both buses through a type 1 cycle conversion. During a type 1
configuration cycle, if the bus number field matches the bridge secondary bus number, the device number field is 1Fh,
and the function number field is 07h, then the bridge generates a special cycle on the secondary bus with a message
that matches the type 1 configuration cycle data. If the bus number is a subordinate bus and not the secondary, then
the bridge passes the type 1 special cycle request through to the secondary interface along with the proper message.
Special cycles are never passed through the bridge. Type 1 configuration cycles with a special cycle request can
propagate in both directions.
3.5 Secondary Clocks
The PCI2050B bridge provides 10 secondary clock outputs (S_CLKOUT[0:9]). Nine are provided for clocking
secondary devices. The tenth clock must be routed back into the PCI2050B S_CLK input to ensure all secondary bus
devices see the same clock. Figure 3−5 is a block diagram of the secondary clock function.