Datasheet

A AS 0 1 0 0 A1A2 A0 0
Start
Condition
ACK
From Slave
ACK
From Slave
Data DataSlave Address
R/W
P7 P6 1 P0 P7 P0 A
Integral Multiples of Two Bytes
P5
t
pv
I
OHT
t
ir
SCL
SDA
Write to
Port
Data Output
Voltage
P5 Output
Voltage
P5 Pullup
Output
Current
INT
ACK
From Slave
Data A0
and B0
Valid
1
2 3 4
5
6 7 8 1 2 3 4 5
6
7 8 1 2 3 4 5 6 7 8
I
OH
A AS 0 1 0 0 A1A2 A0 1
ACK
From Slave
ACK
From Master
R/W
P7 P6 P0 P7
ACK
From Master
t
su
t
ir
SCL
SDA
Read From
Port
Data Into
Port
INT
P5 P4 P3 P2 P1 AP0
t
ir
t
iv
P7 to P0
A low-to-high transition of SDA while SCL is high is defined as the stop condition (P). The transfer of data can be stopped at any moment by
a stop condition. When this occurs, data present at the latest ACK phase is valid (output mode). Input data is lost.
P6 P5 P4 P3 P2 P1
t
h
P7 P6
1
2 3 4
5
6 7 8 1 2 3 4 5
6
7 8 1 2 3 4 5 6 7 8
P7 to P0
PCF8574
www.ti.com ............................................................................................................................................................... SCPS068G – JULY 2001 – REVISED MAY 2008
Figure 1 and Figure 2 show the address and timing diagrams for the write and read modes, respectively.
Figure 1. Write Mode (Output)
Figure 2. Read Mode (Input)
Copyright © 2001 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): PCF8574