Datasheet

Reads
0 0 A2 A1 A00 10 0 A2 A1 A00 1S 0
A A A
R/W
A
PNA
S
R/W
1
MSB LSB
M
SB LSB
Slave Address
Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master transmitter
becomes master receiver, and
slave-receiver becomes
slave-transmitter.
1 2 3 4 5 6 7 8 9
S 0 1 0 0 A
2 A1 A0 1
A 7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 A
I1.x
7 6 5 4 3 2 1 0 A
I0.x
7 6 5 4 3 2 1 0 1
I1.x
P
R
/W
SCL
S
DA
INT
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
t
i
v
t
ir
PCA9555
www.ti.com .........................................................................................................................................................SCPS131E–AUGUST2005–REVISEDMAY2008
ThebusmasterfirstmustsendthePCA9555addresswiththeleast-significantbitsettoalogic0(seeFigure4
fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregisterisaccessed.
Afterarestart,thedeviceaddressissentagain,butthistime,theleast-significantbitissettoalogic1.Data
fromtheregisterdefinedbythecommandbytethenissentbythePCA9555(seeFigure8throughFigure10).
Afterarestart,thevalueoftheregisterdefinedbythecommandbytematchestheregisterbeingaccessedwhen
therestartoccurred.Forexample,ifthecommandbytereferencesInputPort1beforetherestart,andtherestart
occurswhenInputPort0isbeingread,thestoredcommandbytechangestoreferenceInputPort0.Theoriginal
commandbyteisforgotten.Ifasubsequentrestartoccurs,InputPort0isreadfirst.Dataisclockedintothe
registerontherisingedgeoftheACKclockpulse.Afterthefirstbyteisread,additionalbytesmayberead,but
thedatanowreflecttheinformationintheotherregisterinthepair.Forexample,ifInputPort1isread,thenext
bytereadisInputPort0.
DataisclockedintotheregisterontherisingedgeoftheACKclockpulse.Thereisnolimitationonthenumber
ofdatabytesreceivedinonereadtransmission,butwhenthefinalbyteisreceived,thebusmastermustnot
acknowledgethedata.
Figure8.ReadFromRegister
A.TransferofdatacanbestoppedatanytimebyaStopcondition.Whenthisoccurs,datapresentatthelatest
acknowledgephaseisvalid(outputmode).Itisassumedthatthecommandbytepreviouslyhasbeensetto00(read
InputPortregister).
B.Thisfigureeliminatesthecommandbytetransfer,arestart,andslaveaddresscallbetweentheinitialslaveaddress
callandactualdatatransferfromthePport(seeFigure8forthesedetails).
Figure9.ReadInputPortRegister,Scenario1
Copyright©2005–2008,TexasInstrumentsIncorporatedSubmitDocumentationFeedback11
ProductFolderLink(s):PCA9555
Not Recommended for New Designs