Datasheet

Interrupt(INT)Output
BusTransactions
Writes
1 2
S
CL
3 4 5 6 7 8
SDA
A A A
Data 0
R/W
t
pv
9
00
0 0 0 0 0 1
0.7 0
.0
Data 1
1
.7 1.0
A
S 0 1 0 0 A2 A1 A0 0
t
pv
P
Slave
Address
Command Byte Data to Port 0 Data to Port 1
Start Condition
Acknowledge
From Slave
Write to Port
Data Out from Port 1
Data Out from Port 0
Data Valid
Acknowledge
From Slave
Acknowledge
From Slave
1 2
SCL
3
4 5 6 7 8
SDA
A A A
Data 0
Data to Register
R
/W
9
00
0 0 0 0 1 1
MSB L
SB
Data1M
SB LSB
A
D
ata to Register
S 0 1 0 0 A2 A1 A0 0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5
P
Acknowledge
From Slave
Acknowledge
From Slave
Start Condition
Command ByteSlave
Address
Acknowledge
From Slave
PCA9555
SCPS131E–AUGUST2005–REVISEDMAY2008......................................................................................................................................................... www.ti.com
Aninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputsintheinputmode.Aftertime,t
iv
,the
signalINTisvalid.Resettingtheinterruptcircuitisachievedwhendataontheportischangedtotheoriginal
setting,dataisreadfromtheportthatgeneratedtheinterruptorinaStopevent.Resettingoccursintheread
modeattheacknowledge(ACK)bitornotacknowledge(NACK)bitafterthefallingedgeoftheSCLsignal.
InterruptsthatoccurduringtheACKorNACKclockpulsecanbelost(orbeveryshort)duetotheresettingof
theinterruptduringthispulse.EachchangeoftheI/OsafterresettingisdetectedandistransmittedasINT.
Readingfromorwritingtoanotherdevicedoesnotaffecttheinterruptcircuit,andapinconfiguredasanoutput
cannotcauseaninterrupt.ChanginganI/Ofromanoutputtoaninputmaycauseafalseinterrupttooccurifthe
stateofthepindoesnotmatchthecontentsoftheInputPortregister.Becauseeach8-bitportisread
independently,theinterruptcausedbyport0isnotclearedbyareadofport1,orviceversa.
INThasanopen-drainstructureandrequiresapullupresistortoV
CC
.
DataisexchangedbetweenthemasterandthePCA9555throughwriteandreadcommands.
DataistransmittedtothePCA9555bysendingthedeviceaddressandsettingtheleast-significantbittoalogic0
(seeFigure4fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregister
receivesthedatathatfollowsthecommandbyte.
TheeightregisterswithinthePCA9555areconfiguredtooperateasfourregisterpairs.Thefourpairsareinput
ports,outputports,polarityinversionports,andconfigurationports.Aftersendingdatatooneregister,thenext
databyteissenttotheotherregisterinthepair(seeFigure6andFigure7).Forexample,ifthefirstbyteissent
tooutputport(register3),thenextbyteisstoredinOutputPort0(register2).
Thereisnolimitationonthenumberofdatabytessentinonewritetransmission.Inthisway,each8-bitregister
maybeupdatedindependentlyoftheotherregisters.
Figure6.WritetoOutputPortRegisters
Figure7.WritetoConfigurationRegisters
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Not Recommended for New Designs