Datasheet

InterruptOutput(INT)
BusTransactions
Writes
SCL
Start Condition
Data 1 Valid
SDA
Write to Port
Data Out
From Port
R/W ACK From Slave
ACK From Slave
ACK From Slave
1
98765432
Data 1
1A20
1S 00 A1 A0 0 A 0000000 A A P
t
pv
Data to PortCommand ByteSlave Address
SCL
SDA
Data to
Register
Start Condition R/W ACK From Slave ACK From Slave ACK From Slave
1 98765432
Data1/0A20 1S 00 A1 A0 0 A 1000000 A A P
Data to RegisterCommand ByteSlave Address
PCA9554
www.ti.com ........................................................................................................................................................SCPS128B–JULY2006–REVISEDAUGUST2008
Aninterruptisgeneratedbyanyrisingorfallingedgeoftheportinputsintheinputmode.Aftertimet
iv
,thesignal
INTisvalid.Resettingtheinterruptcircuitisachievedwhendataontheportischangedtotheoriginalsetting,
anddataisreadfromtheportthatgeneratedtheinterruptorinaStopevent.Resettingoccursinthereadmode
attheacknowledge(ACK)bitornotacknowledge(NACK)bitaftertherisingedgeoftheSCLsignal.Interrupts
thatoccurduringtheACKorNACKclockpulsecanbelost(orbeveryshort)duetotheresettingoftheinterrupt
duringthispulse.EachchangeoftheI/OsafterresettingisdetectedandistransmittedasINT.
Readingfromorwritingtoanotherdevicedoesnotaffecttheinterruptcircuit,andapinconfiguredasanoutput
cannotcauseaninterrupt.ChanginganI/Ofromanoutputtoaninputmaycauseafalseinterrupttooccurifthe
stateofthepindoesnotmatchthecontentsoftheInputPortregister.
INThasanopen-drainstructureandrequiresapullupresistortoV
CC
.
DataisexchangedbetweenthemasterandPCA9554throughwriteandreadcommands.
DataistransmittedtothePCA9554bysendingthedeviceaddressandsettingtheleast-significantbittoalogic0
(seeFigure4fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregister
receivesthedatathatfollowsthecommandbyte.Thereisnolimitationonthenumberofdatabytessentinone
writetransmission.
Figure6.WritetoOutputPortRegister
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Figure7.WritetoConfigurationorPolarityInversionRegisters
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