Datasheet

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A AS 1 1 1 0 A2 A1 A0 0
Start Condition
SDA
R/W ACK From Slave ACK From Slave
P
B0B1B2B3B4B5B6B7
Stop Condition
Slave Address
Control Register
Reads
AS 1 1 1 0 A2 A1 A0 1
SDA PB3 B2 B1 B0
Start Condition R/W ACK From Slave NACK From Master Stop Condition
Slave Address
Control Register
B7 B6 B5 B4 NA
PCA9548A
8-CHANNELI
2
CSWITCH
WITHRESET
SCPS143C–OCTOBER2006–REVISEDJUNE2007
Figure7.WritetoControlRegister
ThebusmasterfirstmustsendthePCA9548AaddresswiththeLSBsettoalogic1(seeFigure4fordevice
address).ThecommandbyteissentaftertheaddressanddetermineswhichSCn/SDnchannelisaccessed.
Afterarestart,thedeviceaddressissentagain,butthistime,theLSBissettoalogic1.Datafromthe
SCn/SDnchanneldefinedbythecommandbytethenissentbythePCA9548A(seeFigure8).Afterarestart,
thevalueoftheSCn/SDnchanneldefinedbythecommandbytematchestheSCn/SDnchannelbeingaccessed
whentherestartoccurred.DataisclockedintotheSCn/SDnchannelontherisingedgeoftheACKclockpulse.
Thereisnolimitationonthenumberofdatabytesreceivedinonereadtransmission,butwhenthefinalbyteis
received,thebusmastermustnotacknowledgethedata.
Figure8.ReadFromControlRegister
9
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