Datasheet

V
CC
CLK
D Q
FF
Configuration
Register
Data From
Shift Register
Data From
Shift Register
Q
Write Configuration
Pulse
CLK
D Q
FF
Q
Write Pulse
Output Port
Register
Q1
Q2
GND
I/O Pin
Output Port
Register Data
CLK
D Q
FF
Q
Input Port
Register
Read Pulse
CLK
D Q
FF
Q
Polarity Inversion
Register
Write Polarity
Pulse
Input Port
Register Data
Polarity
Register Data
To INT
Data From
Shift Register
I/O Port
PCA9535
www.ti.com ........................................................................................................................................................... SCPS129I – AUGUST 2005 – REVISED MAY 2008
SIMPLIFIED SCHEMATIC OF P-PORT I/Os
(1)
(1) At power-on reset, all registers return to default values.
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above V
CC
to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either V
CC
or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
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