Datasheet

PCA9534
SCPS124G –SEPTEMBER 2006–REVISED JUNE 2010 www.ti.com
Table 5. Command Byte (continued)
CONTROL
COMMAND POWER-UP
REGISTER BITS
REGISTER PROTOCOL
BYTE (HEX) DEFAULT
B1 B0
0 1 0x01 Output Port Read/write byte 1111 1111
1 0 0x02 Polarity Inversion Read/write byte 0000 0000
1 1 0x03 Configuration Read/write byte 1111 1111
Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is
defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level.
Before a read operation, a write transmission is sent with the command byte to let the I
2
C device know that the
Input Port register will be accessed next.
Table 6. Register 0 (Input Port Register)
BIT I7 I6 I5 I4 I3 I2 I1 I0
DEFAULT X X X X X X X X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this
register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 7. Register 1 (Output Port Register)
BIT O7 O6 O5 O4 O3 O2 O1 O0
DEFAULT 1 1 1 1 1 1 1 1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin original polarity is retained.
Table 8. Register 2 (Polarity Inversion Register)
BIT N7 N6 N5 N4 N3 N2 N1 N0
DEFAULT 0 0 0 0 0 0 0 0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1,
the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output.
Table 9. Register 3 (Configuration Register)
BIT C7 C6 C5 C4 C3 C2 C1 C0
DEFAULT 1 1 1 1 1 1 1 1
Power-On Reset
When power (from 0 V) is applied to V
CC
, an internal power-on reset holds the PCA9534 in a reset condition until
V
CC
has reached V
POR
. At that point, the reset condition is released and the PCA9534 registers and I
2
C/SMBus
state machine will initialize to their default states. After that, V
CC
must be lowered to below 0.2 V and then back
up to the operating voltage for a power-reset cycle.
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