Datasheet

OPA657
14
SBOS197E
www.ti.com
the signal gain is –(R
F
/R
G
) while the noise gain for bandwidth
purposes is (1 + R
F
/R
G
). This cuts the noise gain in half,
increasing the minimum stable gain for inverting operation
under these condition to –12 and the equivalent gain band-
width product to 3.2GHz.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an A/D converter — including
additional external capacitance which may be recommended
to improve A/D linearity. A high speed, high open-loop gain
amplifier like the OPA657 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier’s open loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics illustrate Recommended R
S
vs
Capacitive Load and the resulting frequency response at the
load. In this case, a design target of a maximally flat fre-
quency response was used. Lower values of R
S
may be used
if some peaking can be tolerated. Also, operating at higher
gains (than the +10 used in the Typical Characteristics) will
require lower values of R
S
for a minimally peaked frequency
response. Parasitic capacitive loads greater than 2pF can
begin to degrade the performance of the OPA657. Long PC
board traces, unmatched cables, and connections to multiple
devices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA657 output pin
(see Board Layout section).
DISTORTION PERFORMANCE
The OPA657 is capable of delivering a low distortion signal
at high frequencies over a wide range of gains. The distortion
plots in the Typical Characteristics show the typical distortion
under a wide variety of conditions.
Generally, until the fundamental signal reaches very high
frequencies or powers, the 2nd-harmonic will dominate the
distortion with negligible 3rd-harmonic component. Focusing
then on the 2nd-harmonic, increasing the load impedance
improves distortion directly. Remember that the total load
includes the feedback network—in the non-inverting configu-
ration this is sum of R
F
+ R
G
, while in the inverting configura-
tion this is just R
F
(Figure 1). Increasing output voltage swing
increases harmonic distortion directly. A 6dB increase in
output swing will generally increase the 2nd-harmonic 12dB
and the 3rd-harmonic 18dB. Increasing the signal gain will also
increase the 2nd-harmonic distortion. Again a 6dB increase in
gain will increase the 2nd- and 3rd-harmonic by about 6dB
even with a constant output power and frequency. And finally,
the distortion increases as the fundamental frequency in-
creases due to the rolloff in the loop gain with frequency.
Conversely, the distortion will improve going to lower frequen-
cies down to the dominant open loop pole at approximately
100kHz. Starting from the –70dBc 2nd-harmonic for a 5MHz,
2V
PP
fundamental into a 200Ω load at G = +10 (from the
Typical Characteristics), the 2nd-harmonic distortion for fre-
quencies lower than 100kHz will be approximately < –90dBc.
The OPA657 has an extremely low 3rd-order harmonic distor-
tion. This also shows up in the 2-tone 3rd-order intermodulation
spurious (IM3) response curves. The 3rd-order spurious levels
are extremely low (< –80dBc) at low output power levels. The
output stage continues to hold them low even as the fundamen-
tal power reaches higher levels. As the Typical Characteristics
show, the spurious intermodulation powers do not increase as
predicted by a traditional intercept model. As the fundamental
power level increases, the dynamic range does not decrease
significantly. For 2 tones centered at 10MHz, with 4dBm/tone
into a matched 50Ω load (that is, 1V
PP
for each tone at the load,
which requires 4V
PP
for the overall 2-tone envelope at the
output pin), the Typical Characteristics show a 82dBc difference
between the test tone and the 3rd-order intermodulation spuri-
ous levels. This exceptional performance improves further when
operating at lower frequencies and/or higher load impedances.
DC ACCURACY AND OFFSET CONTROL
The OPA657 can provide excellent DC accuracy due to its high
open-loop gain, high common-mode rejection, high power-supply
rejection, and its trimmed input offset voltage (and drift) along with
the negligible errors introduced by the low input bias current. For
the best DC precision, a high-grade version (OPA657UB or
OPA657NB) screens the key DC parameters to an even tighter
limit. Both standard- and high-grade versions take advantage of
a new final test technique to 100% test input offset voltage drift
over temperature. This discussion will use the high-grade typical
and min/max electrical characteristics for illustration, however, an
identical analysis applies to the standard-grade version.
The total output DC offset voltage in any configuration and
temperature will be the combination of a number of possible error
terms. In a JFET part like the OPA657, the input bias current
terms are typically quite low but are unmatched. Using bias
current cancellation techniques, more typical in bipolar input
amplifiers, does not improve output DC offset errors. Errors due
to the input bias current will only become dominant at elevated
temperatures. The OPA657 shows the typical 2X increase in
every 10°C common to JFET-input stage amplifiers. Using the
5pA maximum tested value at 25°C, and a 20°C internal self
heating (see thermal analysis), the maximum input bias current
at 85°C ambient will be 5pA • 2
(105 – 25)/10
= 1280pA.
For noninverting configurations, this term only begins to be
a significant term versus the input offset voltage for source