Datasheet

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SBOS317D − SEPTEMBER 2004 − REVISED AUGUST 2008
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18
The differential receiver is configured as an inverting
summing stage where the outputs of the driver are
cancelled prior to appearing at the output of the receive
amplifiers. This is done by summing the output voltages for
the drive amplifiers and their attenuated and inverted
levels (at the transformer input) into the inverting inputs of
each receiver amplifier. The resistor values are set (see
the circuit on the front page) to give perfect drive signal
cancellation if the drive signal is attenuated by 1/2, going
from the drive amplifier outputs to the transformer input.
The signal received through the transformer has a gain of
1 through the receive amplifiers. Higher gain could easily
be provided by scaling the resistors summing into the
inverting inputs of the receiver amplifiers down while
keeping the same ratio between them.
DUAL-CHANNEL, DIFFERENTIAL ADC DRIVER
Where a low-noise, single-supply, interface to a differential
input +5V ADC is required, the circuit of Figure 11 can
provide a high dynamic range, medium gain interface for
dual high-performance ADCs. The circuit of Figure 11
uses two amplifiers in the differential inverting
configuration. The common-mode voltage is set on the
noninverting inputs to the supply midscale. In this
example, the input signal is coupled in through a 1:2
transformer. This provides both signal gain, single to
differential conversion, and a reduction in noise figure. To
show a 50Ω input impedance at the input to the
transformer, two 200Ω resistors are required on the
transformer secondary. These two resistors are also the
amplifier gain elements. Since the same DC voltage
appears on both inverting nodes in the circuit of Figure 11,
no DC current will flow through the transformer, giving a
DC gain of 1 to the output for this common-mode voltage,
V
CM
.
The circuit of Figure 11 is particularly suitable for a
moderate resolution dual ADC used as I/Q samplers. The
optional 500Ω resistors to ground on each amplifier output
can be added to improve the 2nd- and 3rd-harmonic
distortion by > 15dB if higher dynamic range is required.
The 5mA added output stage current significantly
improves linearity if that is required. The measured
2nd-harmonic distortion is consistently lower than the
3rd-harmonics for this balanced differential design. It is
particularly helpful for this low-power design if there are no
grounds in the signal path after the low-level signal at the
transformer input. The two pull-down resistors do show a
signal path ground and should be connected at the same
physical point to ground, in order to eliminate imbalanced
ground return currents from degrading 2nd-harmonic
distortion.
VIDEO LINE DRIVING
Most video distribution systems are designed with 75Ω
series resistors to drive a matched 75Ω cable. In order to
deliver a net gain of 1 to the 75Ω matched load, the
amplifier is typically set up for a voltage gain of +2,
compensating for the 6dB attenuation of the voltage
divider formed by the series and shunt 75Ω resistors at
either end of the cable.
The circuit of Figure 1 applies to this requirement if all
references to 50Ω resistors are replaced by 75Ω values.
Often, the amplifier gain is further increased to 2.2, which
recovers the additional DC loss of a typical long cable run.
This change would require the gain resistor (R
G
) in
Figure 1 to be reduced from 402Ω to 335Ω. In either case,
both the gain flatness and the differential gain/phase
performance of the OPA4820 will provide exceptional
results in video distribution applications. Differential gain
and phase measure the change in overall small-signal
gain and phase for the color sub-carrier frequency
(3.58MHz in NTSC systems) versus changes in the
large-signal output level (which represents luminance
information in a composite video signal). The OPA4820,
with the typical 150Ω load of a single matched video cable,
shows less than 0.003%/0.06° differential gain/phase
errors over the standard luminance range for a positive
video (negative sync) signal. Similar performance would
be observed for multiple video signals (see Figure 12).