Datasheet
OPA141
OPA2141
OPA4141
www.ti.com
SBOS510B –MARCH 2010–REVISED MAY 2010
THERMAL INFORMATION
OPA141, OPA141,
OPA2141 OPA2141
THERMAL METRIC UNITS
D (SO) DGK (MSOP)
(1)
8 8
q
JA
Junction-to-ambient thermal resistance
(2)
160 180
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
75 55
q
JB
Junction-to-board thermal resistance
(4)
60 130
°C/W
y
JT
Junction-to-top characterization parameter
(5)
9 n/a
y
JB
Junction-to-board characterization parameter
(6)
50 120
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
THERMAL INFORMATION
OPA4141 OPA4141
THERMAL METRIC D (SO) PW (TSSOP)
(1)
UNITS
14 14
q
JA
Junction-to-ambient thermal resistance
(2)
97 135
q
JC(top)
Junction-to-case(top) thermal resistance
(3)
56 45
q
JB
Junction-to-board thermal resistance
(4)
53 66
°C/W
y
JT
Junction-to-top characterization parameter
(5)
19 n/a
y
JB
Junction-to-board characterization parameter
(6)
46 60
q
JC(bottom)
Junction-to-case(bottom) thermal resistance
(7)
n/a n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, y
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, y
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining q
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated 3
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