Datasheet

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SBOS365D − JUNE 2006 − REVISED JUNE 2009
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13
One method for driving an ADC that negates the need
for an output swing down to 0V uses a slightly com-
pressed ADC full-scale input range (FSR). For exam-
ple, the 16-bit ADS8361 (shown in Figure 11) has a
maximum FSR of 0V to 5V, when powered by a +5V
supply and V
REF
of 2.5V. The idea is to match the ADC
input range with the op amp full linear output swing
range; for example, an output range of +0.1 to +4.9V.
The reference output from the ADS8361 ADC is divided
down from 2.5V to 2.4V using a resistive divider. The
ADC FSR then becomes 4.8V
PP
centered on a com-
mon-mode voltage of +2.5V. Current from the ADS8361
reference pin is limited to about ±10µA. Here, 5µA was
used to bias the divider. The resistors must be precise
to maintain the ADC gain accuracy. An additional bene-
fit of this method is the elimination of the negative sup-
ply voltage; it requires no additional power-supply cur-
rent.
An RC network, consisting of R
1
and C
1
, is included be-
tween the op amp and the ADS8361. It not only pro-
vides a high-frequency filter function, but more impor-
tantly serves as a charge reservoir used for charging
the converter internal hold capacitance. This capability
assures that the op amp output linearity is maintained
as the ADC input characteristics change throughout the
conversion cycle. Depending on the particular applica-
tion and ADC, some optimization of the R
1
and C
1
val-
ues may be required for best transient performance.
V
−
C
1
100nF
R
2
10k
Ω
R
1
10k
Ω
NOTE: (1) Suggested value; may require adjustment
based on specific application.
R
3
(1)
100
Ω
R
4
20k
Ω
R
5
480k
Ω
V+
+5V
V
IN
0.1V to 4.9V
ADS8361
16−Bit
100kSPS
OPA365
C
2
(1)
1nF
C
3
1
µ
F
REF IN
+IN
−
IN
+5V
REF OUT
+2.5V
+2.4V
Figure 11. Driving the ADS8361