Datasheet

STE
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
STE,LEAD
1/f
UCxCLK
t
STE,LAG
t
STE,DIS
t
STE,ACC
t
HD,MO
t
LO/HI
t
LO/HI
STE
UCLK
CKPL = 0
CKPL = 1
SOMI
SIMO
t
SU,SI
t
HD,SI
t
VALID,SO
t
STE,LEAD
1/f
UCxCLK
t
LO/HI
t
LO/HI
t
STE,LAG
t
STE,DIS
t
STE,ACC
t
HD,SO
MSP430G2x53
MSP430G2x13
SLAS735J –APRIL 2011–REVISED MAY 2013 www.ti.com
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and
Figure 19)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
t
STE,LEAD
STE lead time, STE low to clock 3 V 50 ns
t
STE,LAG
STE lag time, Last clock to STE high 3 V 10 ns
t
STE,ACC
STE access time, STE low to SOMI data out 3 V 50 ns
STE disable time, STE high to SOMI high
t
STE,DIS
3 V 50 ns
impedance
t
SU,SI
SIMO input data setup time 3 V 15 ns
t
HD,SI
SIMO input data hold time 3 V 10 ns
UCLK edge to SOMI valid,
t
VALID,SO
SOMI output data valid time 3 V 50 75 ns
C
L
= 20 pF
Figure 18. SPI Slave Mode, CKPH = 0
Figure 19. SPI Slave Mode, CKPH = 1
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