Datasheet

MSP430FW429, MSP430FW428
MSP430FW427, MSP430FW425, MSP430FW423
SLAS383E –OCTOBER 2003–REVISED DECEMBER 2013 www.ti.com
Special Function Registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
Interrupt Enable 1 and 2
Address 7 6 5 4 3 2 1 0
00h ACCVIE NMIIE OFIE WDTIE
rw-0 rw-0 rw-0 rw-0
7 6 5 4 3 2 1 0
01h BTIE
rw-0
WDTIE: Watchdog-timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval
timer mode.
OFIE: Oscillator-fault-interrupt enable
NMIIE: Nonmaskable-interrupt enable
ACCVIE: Flash access violation interrupt enable
BTIE: Basic Timer1 interrupt enable
Interrupt Flag Register 1 and 2
Address 7 6 5 4 3 2 1 0
02h NMIIFG OFIFG WDTIFG
rw-0 rw-1 rw-(0)
7 6 5 4 3 2 1 0
03h BTIFG
rw-0
WDTIFG: Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on V
CC
power up or a reset condition at the RST/NMI pin in reset mode
OFIFG: Flag set on oscillator fault
NMIIFG: Set via RST/NMI pin
BTIFG: Basic Timer1 interrupt flag
Module Enable Registers 1 and 2
Address 7 6 5 4 3 2 1 0
04h/05h
Legend rw: Bit can be Read and Written.
rw-0,1: Bit can be Read and Written. It is Reset or Set by PUC.
rw-(0,1): Bit can be Read and Written. It is Reset or Set by POR.
SFR bit is not present in device
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