Datasheet

PJ.5/XOUT
PJSEL0.5
PJDIR.5
PJIN.5
EN
Tomodules
DVSS
PJOUT.5
1
0
DVSS
DVCC
1
D
ToXT1XOUT
PadLogic
Bus
Keeper
Direction
0:Input
1:Output
PJREN.5
01
00
10
11
PJSEL1.5
01
00
10
11
DVSS
DVSS
PJSEL0.4
XT1BYPASS
MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Table 55. Port PJ (PJ.4 and PJ.5) Pin Functions
CONTROL BITS/SIGNALS
(1)
PIN NAME (P7.x) x FUNCTION
XT1
PJDIR.x PJSEL1.5 PJSEL0.5 PJSEL1.4 PJSEL0.4
BYPASS
PJ.4/XIN 4 PJ.4 (I/O) I: 0; O: 1 X X 0 0 X
XIN crystal mode
(2)
X X X 0 1 0
XIN bypass mode
(2)
X X X 0 1 1
PJ.5/XOUT 5 PJ.5 (I/O) I: 0; O: 1 0 0 0 0 X
XOUT crystal mode
X X X 0 1 0
(3)
PJ.5 (I/O)
(4)
I: 0; O: 1 X X 0 1 1
(1) X = Don't care
(2) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(3) Setting PJSEL1.4 = 0 and PJSEL0.4 = 1 causes the general-purpose I/O to be disabled. When XT1BYPASS = 0, PJ.4 and PJ.5 are
configured for crystal operation and PJSEL1.5 and PJSEL0.5 are do not care. When XT1BYPASS = 1, PJ.4 is configured for bypass
operation and PJ.5 is configured as general-purpose I/O.
(4) When PJ.4 is configured in bypass mode, PJ.5 is configured as general-purpose I/O.
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