Datasheet

SDA
SCL
t
HD,DAT
t
SU,DAT
t
HD,STA
t
HIGH
t
LOW
t
BUF
t
HD,STA
t
SU,STA
t
SP
t
SU,STO
MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 11)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
Internal: SMCLK, ACLK
f
eUSCI
eUSCI input clock frequency External: UCLK f
SYSTEM
MHz
Duty cycle = 50% ± 10%
f
SCL
SCL clock frequency 2 V, 3 V 0 400 kHz
f
SCL
= 100 kHz 4.0
t
HD,STA
Hold time (repeated) START 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
f
SCL
= 100 kHz 4.7
t
SU,STA
Setup time for a repeated START 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
t
HD,DAT
Data hold time 2 V, 3 V 0 ns
t
SU,DAT
Data setup time 2 V, 3 V 250 ns
f
SCL
= 100 kHz 4.0
t
SU,STO
Setup time for STOP 2 V, 3 V µs
f
SCL
> 100 kHz 0.6
UCGLITx = 0 50 600 ns
UCGLITx = 1 25 300 ns
Pulse duration of spikes suppressed by
t
SP
2 V, 3 V
input filter
UCGLITx = 2 12.5 150 ns
UCGLITx = 3 6.25 75 ns
UCCLTOx = 1 27 ms
t
TIMEOUT
Clock low timeout UCCLTOx = 2 2 V, 3 V 30 ms
UCCLTOx = 3 33 ms
Figure 11. I2C Mode Timing
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