Datasheet

Clock
System
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
PJ.4/XIN PJ.5/XOUT
JTAG/
SBW
Interface
DMA
3 Channel
Power
Management
SVS
SYS
Watchdog
MPY32
TA0
TA1
(2) Timer_A
3 CC
Registers
TB0
(1) Timer_B
3 CC
Registers
DVCC
DVSS
AVCC
AVSS
RST/NMI/SBWTDIO
RTC_B
Comp_D
10 channels
VCORE
MAB
MDB
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
I/O Ports
P1/P2
1×8 I/Os
1
Interrupt
& Wakeup
PA
1×11 I/Os
×3 I/Os
PA
P1.x P2.x
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Boot
ROM
Memory
Protection
Unit
16 KB
8 KB
FRAM
(’5736, ’5726)
(’5732, ‘5722)
1 KB
RAM
REF
Clock
System
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
PJ.4/XIN PJ.5/XOUT
JTAG/
SBW
Interface
DMA
3 Channel
Power
Management
SVS
SYS
Watchdog
MPY32
TA0
TA1
(2) Timer_A
3 CC
Registers
TB0
(1) Timer_B
3 CC
Registers
ADC10_B
200KSPS
8 channels
(6 ext/2 int)
10 Bit
DVCC
DVSS
AVCC
AVSS
RST/NMI/SBWTDIO
RTC_B
Comp_D
10 channels
VCORE
MAB
MDB
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
I/O Ports
P1/P2
1×8 I/Os
1
Interrupt
& Wakeup
PA
1×11 I/Os
×3 I/Os
PA
P1.x P2.x
REF
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Boot
ROM
Memory
Protection
Unit
16 KB
8 KB
FRAM
(’5738, ’5728)
(’5734, ‘5724)
4 KB
(’5730, ‘5720)
1 KB
RAM
MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
Functional Block Diagram –
MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE, MSP430FR5738IYQD
Functional Block Diagram –
MSP430FR5722IRGE, MSP430FR5726IRGE,
MSP430FR5732IRGE, MSP430FR5736IRGE
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