Datasheet

MSP430FR573x
MSP430FR572x
www.ti.com SLAS639H –JULY 2011–REVISED SEPTEMBER 2013
Table 54. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS
(1)
PIN NAME (PJ.x) x FUNCTION
PJDIR.x PJSEL1.x PJSEL0.x
PJ.0/TDO/TB0OUTH/SMCLK/CD6 0 PJ.0 (I/O)
(2)
I: 0; O: 1 0 0
TDO
(3)
X X X
TB0OUTH 0
0 1
SMCLK 1
CD6 X 1 1
PJ.1/TDI/TCLK/TB1OUTH/MCLK/CD7 1 PJ.1 (I/O)
(2)
I: 0; O: 1 0 0
TDI/TCLK
(3) (4)
X X X
TB1OUTH 0
0 1
MCLK 1
CD7 X 1 1
PJ.2/TMS/TB2OUTH/ACLK/CD8 2 PJ.2 (I/O)
(2)
I: 0; O: 1 0 0
TMS
(3) (4)
X X X
TB2OUTH 0
0 1
ACLK 1
CD8 X 1 1
PJ.3/TCK/CD9 3 PJ.3 (I/O)
(2)
I: 0; O: 1 0 0
TCK
(3) (4)
X X X
CD9 X 1 1
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made by the SYS module or by the Spy-Bi-Wire four-wire
entry sequence. PJSEL1.x and PJSEL0.x have no effect in these cases.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
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