Datasheet

Clock
System
16 KB
8 KB
FRAM
(’5737, ’5727)
(’5733, ‘5723)
1 KB
RAM
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
PJ.4/XIN PJ.5/XOUT
JTAG/
SBW
Interface
DMA
3 Channel
Power
Management
SVS
SYS
Watchdog
MPY32
TA0
TA1
(2) Timer_A
3 CC
Registers
TB0
TB1
TB2
(3) Timer_B
3 CC
Registers
DVCC
DVSS
AVCC
AVSS
RST/NMI/SBWTDIO
RTC_B
REF
VCORE
MAB
MDB
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
PA
P1.x P2.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
PB
P3.x
P4.x
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Boot
ROM
Memory
Protection
Unit
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
16 channels
Clock
System
16 KB
8 KB
FRAM
(’5739, ’5729)
(’5735, ‘5725)
4 KB
(’5731, ‘5721)
1 KB
RAM
MCLK
ACLK
SMCLK
CPUXV2
and
Working
Registers
EEM
(S: 3+1)
PJ.4/XIN PJ.5/XOUT
JTAG/
SBW
Interface
DMA
3 Channel
Power
Management
SVS
SYS
Watchdog
MPY32
TA0
TA1
(2) Timer_A
3 CC
Registers
TB0
TB1
TB2
(3) Timer_B
3 CC
Registers
ADC10_B
200KSPS
14 channels
(12 ext/2 int)
10 Bit
DVCC
DVSS
AVCC
AVSS
RST/NMI/SBWTDIO
RTC_B
Comp_D
16 channels
VCORE
MAB
MDB
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
PA
P1.x P2.x
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
PB
P3.x
P4.x
REF
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
Boot
ROM
Memory
Protection
Unit
eUSCI_A1:
UART,
IrDA, SPI
MSP430FR573x
MSP430FR572x
SLAS639H –JULY 2011–REVISED SEPTEMBER 2013 www.ti.com
Functional Block Diagram –
MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA
Functional Block Diagram –
MSP430FR5723IRHA, MSP430FR5727IRHA,
MSP430FR5733IRHA, MSP430FR5737IRHA
4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated