Datasheet
Table Of Contents
- features
- description
- Available Options
- pin designation, DL package
- pin designation, RGZ package
- functional block diagram
- Terminal Functions
- short-form description
- absolute maximum ratings
- recommended operating conditions
- electrical characteristics
- supply current into AVCC + DVCC excluding external current
- Schmitt-trigger inputs − Ports P1, P2, P5, and P6; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
- inputs Px.x, TAx
- leakage current − Ports P1, P2, P5, and P6
- outputs − Ports P1, P2, P5, and P6
- output frequency
- wake-up LPM3
- RAM
- LCD_A
- POR/brownout reset (BOR)
- DCO
- crystal oscillator, LFXT1 oscillator
- SD16_A, power supply and recommended operating conditions
- SD16_A, input range
- SD16_A, performance
- SD16_A, temperature sensor
- SD16_A, built-in voltage reference
- SD16_A, reference output buffer
- SD16_A, external reference input
- 12-bit DAC, supply specifications
- 12-bit DAC, linearity specifications
- 12-bit DAC, output specifications
- 12-bit DAC, reference input specifications
- 12-bit DAC, dynamic specifications
- operational amplifier OA, supply specifications
- operational amplifier OA, input/output specifications
- operational amplifier OA, dynamic specifications
- switches to ground
- flash memory
- JTAG interface
- JTAG fuse
- input/output schematics
- Port P1 pin schematic: P1.0, P1.1, input/output with Schmitt−trigger
- Port P1 pin schematic: P1.2, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.3, P1.5, P1.7, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.4, input/output with Schmitt−trigger and analog functions
- Port P1 pin schematic: P1.6, input/output with Schmitt−trigger and analog functions
- Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt−trigger, LCD and analog functions
- Port P2 pin schematic: P2.2 to P2.7, input/output with Schmitt−trigger, LCD and analog functions
- Port P5 pin schematic: P5.0, P5.1, P5.5 to P5.7, input/output with Schmitt−trigger and LCDfunctions
- Port P5 pin schematic: P5.2 to P5.4, input/output with Schmitt−trigger and LCD functions
- Port P6 pin schematic: P6.0, P6.2, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.1, P6.3, input/output with Schmitt−trigger and analog functions
- Port P6 pin schematic: P6.4 to P6.7, input/output with Schmitt−trigger and analog functions
- JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
- JTAG fuse check mode
- Data Sheet Revision History
MSP430FG42x0
MIXED SIGNAL MICROCONTROLLER
SLAS556A − JULY 2007 − REVISED AUGUST 2007
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
V
Reference input
DAC12IR=0 (see Notes 1 and 2)
2 2V/3V
AV
CC
/3 AV
CC
+0.2
V
V
REF
Reference
input
voltage range
DAC12IR=1 (see Notes 3 and 4)
2.2V/3V
AV
CC
AV
CC
+0.2
V
Ri
Reference input
DAC12IR=0
2 2V/3V
20 MΩ
Ri
(VREF)
Reference
input
resistance
DAC12IR=1
2.2V/3V
40 48 56 kΩ
NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AV
CC
).
2. The maximum voltage applied at reference input voltage terminal V
REF
= [AV
CC
− V
E(O)
] / [3*(1 + E
G
)].
3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV
CC
).
4. The maximum voltage applied at reference input voltage terminal V
REF
= [AV
CC
− V
E(O)
] / (1 + E
G
).
12-bit DAC, dynamic specifications, V
REF,DAC12
= AV
CC
, DAC12IR = 1 (see Figure 16 and Figure 17)
PARAMETER TEST CONDITIONS V
CC
MIN TYP MAX UNIT
DAC12
DAC12_xDAT = 800h,
DAC12AMPx=0 → {2, 3, 4} 60 120
t
ON
DAC12
on time
DAC12
_
xDAT
=
800h
,
Error
V(O)
< ±0.5 LSB
DAC12AMPx=0 → {5, 6}
2.2V/3V
15 30
μs
t
ON
on time
Error
V(O)
<
±0.5
LSB
(see Note 1,Figure 16)
DAC12AMPx=0 → 7
2.2V/3V
6 12
μs
Settling time
DAC12 xDAT
DAC12AMPx=2 100 200
t
S
(
FS
)
Settling time,
full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
40 80
μs
t
S(FS)
full scale 80h→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
15 30
μs
Settling time
DAC12_xDAT =
DAC12AMPx=2 5
t
S
(
C-C
)
Settling time,
code to code
DAC12
_
xDAT
=
3F8h→ 408h→ 3F8h
DAC12AMPx=3,5
2.2V/3V
2
μs
t
S(C
-
C)
code to code
3F8h→
408h→
3F8h
BF8h→ C08h→ BF8h
DAC12AMPx=4,6,7
2.2V/3V
1
μs
DAC12 xDAT
DAC12AMPx=2 0.05 0.12
SR Slew rate
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
0.35 0.7
V/μs
SR
Slew
rate
80h→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
1.5 2.7
V/μs
DAC12 xDAT
DAC12AMPx=2 10
Glitch energy, full scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx=3,5
2.2V/3V
10
nV-s
Glitch
energy,
full
scale
80h→ F7Fh→ 80h
DAC12AMPx=4,6,7
2.2V/3V
15
nV s
NOTES: 1. R
Load
and C
Load
connected to AV
SS
(not AV
CC
/2) in Figure 16.
2. Slew rate applies to output voltage steps ≥ 200mV.
R
Load
AV
CC
C
Load
= 100pF
2
DAC Output
R
O/P(DAC12.x)
I
Load
Conversion 1 Conversion 2
V
OUT
Conversion 3
Glitch
Energy
+/− 1/2 LSB
+/− 1/2 LSB
t
settleLH
t
settleHL
= 3 kΩ
Figure 16. Settling Time and Glitch Energy Testing