Datasheet

MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590L –MARCH 2009–REVISED MAY 2013 www.ti.com
Table 3. Terminal Functions (continued)
TERMINAL
NO. I/O
(1)
DESCRIPTION
NAME
PN RGC YFF ZQE
USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to
PUR 63 51 G2 B7 I/O invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See USB BSL
for more information.
General-purpose digital I/O - controlled by USB control register
PU.1/DM 64 52 G1 A8 I/O
USB data terminal DM
VBUS 65 53 F2 A7 USB LDO input (connect to USB power source)
VUSB 66 54 F1 A6 USB LDO output
V18 67 55 E2 B6 USB regulated power (internal use only, no external current loading)
AVSS2 68 56 D2 A5 Analog ground supply
General-purpose digital I/O
P5.2/XT2IN 69 57 E1 B5 I/O
Input terminal for crystal oscillator XT2
General-purpose digital I/O
P5.3/XT2OUT 70 58 D1 B4 I/O
Output terminal of crystal oscillator XT2
Test mode pin – Selects four wire JTAG operation.
TEST/SBWTCK
(3)
71 59 E3 A4 I
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
General-purpose digital I/O
PJ.0/TDO
(4)
72 60 D3 C5 I/O
JTAG test data output port
General-purpose digital I/O
PJ.1/TDI/TCLK
(4)
73 61 D4 C4 I/O
JTAG test data input or test clock input
General-purpose digital I/O
PJ.2/TMS
(4)
74 62 C1 A3 I/O
JTAG test mode select
General-purpose digital I/O
PJ.3/TCK
(4)
75 63 C2 B3 I/O
JTAG test clock
Reset input active low
(6)
RST/NMI/SBWTDIO
(5)
76 64 D5 A2 I/O
Non-maskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
General-purpose digital I/O
P6.0/CB0/A0 77 1 B1 A1 I/O
Comparator_B input CB0
Analog input A0 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.1/CB1/A1 78 2 C3 B2 I/O
Comparator_B input CB1
Analog input A1 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.2/CB2/A2 79 3 A1 B1 I/O
Comparator_B input CB2
Analog input A2 – ADC (not available on F551x devices)
General-purpose digital I/O
P6.3/CB3/A3 80 4 C4 C2 I/O
Comparator_B input CB3
Analog input A3 – ADC (not available on F551x devices)
Reserved N/A N/A N/A
(7)
QFN Pad N/A Pad N/A N/A QFN package pad connection to V
SS
recommended.
(3) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(4) See JTAG Operation for use with JTAG function.
(5) See Bootstrap Loader (BSL) and JTAG Operation for use with BSL and JTAG functions.
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.
(7) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
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Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513