Datasheet
MSP430F5529, MSP430F5528, MSP430F5527, MSP430F5526
MSP430F5525, MSP430F5524, MSP430F5522, MSP430F5521
MSP430F5519, MSP430F5517, MSP430F5515, MSP430F5514, MSP430F5513
SLAS590L –MARCH 2009–REVISED MAY 2013
www.ti.com
Port Mapping Controller (Link to User's Guide)
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4 (see
Table 10). Table 11 shows the default mappings.
Table 10. Port Mapping Mnemonics and Functions
VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION
0 PM_NONE None DVSS
PM_CBOUT0 - Comparator_B output
1
PM_TB0CLK TB0 clock input
PM_ADC12CLK - ADC12CLK
2
PM_DMAE0 DMAE0 input
PM_SVMOUT - SVM output
3
PM_TB0OUTH TB0 high impedance input TB0OUTH
4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0
5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1
6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2
7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3
8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4
9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5
10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6
PM_UCA1RXD USCI_A1 UART RXD (Direction controlled by USCI - input)
11
PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI)
PM_UCA1TXD USCI_A1 UART TXD (Direction controlled by USCI - output)
12
PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI)
PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI)
13
PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI)
PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI)
14
PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI)
PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI)
15
PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI)
PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI)
16
PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI)
17 PM_CBOUT1 None Comparator_B output
18 PM_MCLK None MCLK
19 - 30 Reserved None DVSS
Disables the output driver as well as the input Schmitt-trigger to prevent
31 (0FFh)
(1)
PM_ANALOG
parasitic cross currents when applying analog signals.
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored
resulting in a read out value of 31.
26 Submit Documentation Feedback Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524
MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513